Lines Matching +full:rx +full:- +full:ctrl
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
52 { true, "RTES", "RX FSM Timeout Error" },
95 { true, "RXCES", "MTL RX Memory Error" },
96 { true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
97 { true, "RXUES", "MTL RX Memory Error" },
103 { true, "RPCES", "MTL RX Parser Memory Error" },
104 { true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
105 { true, "RPUES", "MTL RX Parser Memory Error" },
203 return -EINVAL; in dwmac5_safety_feat_config()
211 if (safety_feat_cfg->tsoee) in dwmac5_safety_feat_config()
213 if (safety_feat_cfg->mrxpee) in dwmac5_safety_feat_config()
214 value |= MRXPEE; /* MTL RX Parser ECC */ in dwmac5_safety_feat_config()
215 if (safety_feat_cfg->mestee) in dwmac5_safety_feat_config()
217 if (safety_feat_cfg->mrxee) in dwmac5_safety_feat_config()
218 value |= MRXEE; /* MTL RX FIFO ECC */ in dwmac5_safety_feat_config()
219 if (safety_feat_cfg->mtxee) in dwmac5_safety_feat_config()
225 value |= RPCEIE; /* RX Parser Memory Correctable Error */ in dwmac5_safety_feat_config()
227 value |= RXCEIE; /* RX Memory Correctable Error */ in dwmac5_safety_feat_config()
242 if (safety_feat_cfg->prtyen) in dwmac5_safety_feat_config()
244 if (safety_feat_cfg->tmouten) in dwmac5_safety_feat_config()
250 if (safety_feat_cfg->edpp) in dwmac5_safety_feat_config()
261 if (safety_feat_cfg->epsi) in dwmac5_safety_feat_config()
276 return -EINVAL; in dwmac5_safety_feat_irq_status()
320 return -EINVAL; in dwmac5_safety_feat_dump()
322 return -EINVAL; in dwmac5_safety_feat_dump()
357 for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) { in dwmac5_rxp_update_single_entry()
358 int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i; in dwmac5_rxp_update_single_entry()
368 val = *((u32 *)&entry->val + i); in dwmac5_rxp_update_single_entry()
402 for (i = count - 1; i >= 0; i--) { in dwmac5_rxp_get_next_entry()
406 if (!entry->in_use) in dwmac5_rxp_get_next_entry()
409 if (entry->in_hw) in dwmac5_rxp_get_next_entry()
412 if (entry->is_last) in dwmac5_rxp_get_next_entry()
415 if (entry->is_frag) in dwmac5_rxp_get_next_entry()
418 if (entry->prio < curr_prio) in dwmac5_rxp_get_next_entry()
421 if (entry->prio < min_prio) { in dwmac5_rxp_get_next_entry()
422 min_prio = entry->prio; in dwmac5_rxp_get_next_entry()
441 /* Force disable RX */ in dwmac5_rxp_config()
446 /* Disable RX Parser */ in dwmac5_rxp_config()
454 entry->in_hw = false; in dwmac5_rxp_config()
463 curr_prio = entry->prio; in dwmac5_rxp_config()
464 frag = entry->frag_ptr; in dwmac5_rxp_config()
468 entry->val.af = 0; in dwmac5_rxp_config()
469 entry->val.rf = 0; in dwmac5_rxp_config()
470 entry->val.nc = 1; in dwmac5_rxp_config()
471 entry->val.ok_index = nve + 2; in dwmac5_rxp_config()
478 entry->table_pos = nve++; in dwmac5_rxp_config()
479 entry->in_hw = true; in dwmac5_rxp_config()
481 if (frag && !frag->in_hw) { in dwmac5_rxp_config()
485 frag->table_pos = nve++; in dwmac5_rxp_config()
486 frag->in_hw = true; in dwmac5_rxp_config()
496 if (!entry->is_last) in dwmac5_rxp_config()
503 entry->table_pos = nve++; in dwmac5_rxp_config()
511 /* Enable RX Parser */ in dwmac5_rxp_config()
515 /* Re-enable RX */ in dwmac5_rxp_config()
528 if (!cfg->available) in dwmac5_flex_pps_config()
529 return -EINVAL; in dwmac5_flex_pps_config()
531 return -EBUSY; in dwmac5_flex_pps_config()
533 return -EINVAL; in dwmac5_flex_pps_config()
548 writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index)); in dwmac5_flex_pps_config()
551 cfg->start.tv_nsec = (cfg->start.tv_nsec * 1000) / 465; in dwmac5_flex_pps_config()
552 writel(cfg->start.tv_nsec, ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index)); in dwmac5_flex_pps_config()
554 period = cfg->period.tv_sec * 1000000000; in dwmac5_flex_pps_config()
555 period += cfg->period.tv_nsec; in dwmac5_flex_pps_config()
560 return -EINVAL; in dwmac5_flex_pps_config()
562 writel(period - 1, ioaddr + MAC_PPSx_INTERVAL(index)); in dwmac5_flex_pps_config()
566 return -EINVAL; in dwmac5_flex_pps_config()
568 writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index)); in dwmac5_flex_pps_config()
578 u32 ctrl; in dwmac5_est_write() local
582 ctrl = (reg << ADDR_SHIFT); in dwmac5_est_write()
583 ctrl |= gcl ? 0 : GCRR; in dwmac5_est_write()
585 writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL); in dwmac5_est_write()
587 ctrl |= SRWO; in dwmac5_est_write()
588 writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL); in dwmac5_est_write()
591 ctrl, !(ctrl & SRWO), 100, 5000); in dwmac5_est_write()
598 u32 ctrl; in dwmac5_est_configure() local
600 ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false); in dwmac5_est_configure()
601 ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false); in dwmac5_est_configure()
602 ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false); in dwmac5_est_configure()
603 ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false); in dwmac5_est_configure()
604 ret |= dwmac5_est_write(ioaddr, CTR_LOW, cfg->ctr[0], false); in dwmac5_est_configure()
605 ret |= dwmac5_est_write(ioaddr, CTR_HIGH, cfg->ctr[1], false); in dwmac5_est_configure()
609 for (i = 0; i < cfg->gcl_size; i++) { in dwmac5_est_configure()
610 ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i], true); in dwmac5_est_configure()
615 ctrl = readl(ioaddr + MTL_EST_CONTROL); in dwmac5_est_configure()
616 ctrl &= ~PTOV; in dwmac5_est_configure()
617 ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT; in dwmac5_est_configure()
618 if (cfg->enable) in dwmac5_est_configure()
619 ctrl |= EEST | SSWL; in dwmac5_est_configure()
621 ctrl &= ~EEST; in dwmac5_est_configure()
623 writel(ctrl, ioaddr + MTL_EST_CONTROL); in dwmac5_est_configure()
626 if (cfg->enable) in dwmac5_est_configure()
627 ctrl = (IECGCE | IEHS | IEHF | IEBE | IECC); in dwmac5_est_configure()
629 ctrl = 0; in dwmac5_est_configure()
631 writel(ctrl, ioaddr + MTL_EST_INT_EN); in dwmac5_est_configure()
640 u32 txqcnt_mask = (1 << txqcnt) - 1; in dwmac5_est_irq_status()
654 x->mtl_est_cgce++; in dwmac5_est_irq_status()
661 x->mtl_est_hlbs++; in dwmac5_est_irq_status()
682 x->mtl_est_hlbf++; in dwmac5_est_irq_status()
694 x->mtl_est_btrlm++; in dwmac5_est_irq_status()
696 x->mtl_est_btre++; in dwmac5_est_irq_status()
720 cfg->fpe_csr = EFPE; in dwmac5_fpe_configure()
723 value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; in dwmac5_fpe_configure()
726 cfg->fpe_csr = 0; in dwmac5_fpe_configure()
728 writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); in dwmac5_fpe_configure()
769 u32 value = cfg->fpe_csr; in dwmac5_fpe_send_mpacket()