Lines Matching defs:ethqos
104 int (*configure_func)(struct qcom_ethqos *ethqos);
118 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
120 return readl(ethqos->rgmii_base + offset);
123 static void rgmii_writel(struct qcom_ethqos *ethqos,
126 writel(value, ethqos->rgmii_base + offset);
129 static void rgmii_updatel(struct qcom_ethqos *ethqos,
134 temp = rgmii_readl(ethqos, offset);
136 rgmii_writel(ethqos, temp, offset);
141 struct qcom_ethqos *ethqos = priv;
142 struct device *dev = ðqos->pdev->dev;
146 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
148 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
150 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
152 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
154 rgmii_readl(ethqos, SDC4_STATUS));
156 rgmii_readl(ethqos, SDCC_USR_CTL));
158 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
160 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
162 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
171 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
175 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
179 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
183 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
187 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
190 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
192 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
295 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
297 struct device *dev = ðqos->pdev->dev;
302 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
306 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
310 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
314 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
317 if (!ethqos->has_emac_ge_3) {
318 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
321 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
327 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
338 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
344 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
355 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
358 if (!ethqos->has_emac_ge_3) {
359 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
362 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
365 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
368 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
376 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
378 struct device *dev = ðqos->pdev->dev;
383 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
384 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
390 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
394 if (ethqos->rgmii_config_loopback_en)
400 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
403 switch (ethqos->speed) {
405 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
407 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
409 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
412 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
414 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
417 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
419 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
421 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
428 if (ethqos->has_emac_ge_3) {
430 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
434 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
437 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
440 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
445 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
447 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
450 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
452 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
454 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
456 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
458 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
460 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
463 if (ethqos->has_emac_ge_3)
464 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
468 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
472 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
474 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
477 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
480 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
485 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
487 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
490 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
492 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
494 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
496 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
498 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
501 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
503 if (ethqos->has_emac_ge_3)
504 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
508 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
511 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
513 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
516 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
519 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
523 dev_err(dev, "Invalid speed %d\n", ethqos->speed);
530 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
532 struct device *dev = ðqos->pdev->dev;
537 for (i = 0; i < ethqos->num_por; i++)
538 rgmii_writel(ethqos, ethqos->por[i].value,
539 ethqos->por[i].offset);
540 ethqos_set_func_clk_en(ethqos);
545 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
549 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
552 if (ethqos->has_emac_ge_3) {
553 if (ethqos->speed == SPEED_1000) {
554 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
555 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
556 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
558 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
559 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
564 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
568 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
571 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
573 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
577 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
582 if (!ethqos->has_emac_ge_3)
583 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
589 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
598 if (ethqos->speed == SPEED_1000)
599 ethqos_dll_configure(ethqos);
601 ethqos_rgmii_macro_init(ethqos);
609 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
613 val = readl(ethqos->mac_base + MAC_CTRL_REG);
615 switch (ethqos->speed) {
618 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
628 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
635 writel(val, ethqos->mac_base + MAC_CTRL_REG);
640 static int ethqos_configure(struct qcom_ethqos *ethqos)
642 return ethqos->configure_func(ethqos);
647 struct qcom_ethqos *ethqos = priv;
649 ethqos->speed = speed;
650 ethqos_update_link_clk(ethqos, speed);
651 ethqos_configure(ethqos);
656 struct qcom_ethqos *ethqos = priv;
659 ret = phy_init(ethqos->serdes_phy);
663 ret = phy_power_on(ethqos->serdes_phy);
667 return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
672 struct qcom_ethqos *ethqos = priv;
674 phy_power_off(ethqos->serdes_phy);
675 phy_exit(ethqos->serdes_phy);
680 struct qcom_ethqos *ethqos = priv;
684 ret = clk_prepare_enable(ethqos->link_clk);
686 dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
695 ethqos_set_func_clk_en(ethqos);
697 clk_disable_unprepare(ethqos->link_clk);
732 struct qcom_ethqos *ethqos;
748 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
749 if (!ethqos)
752 ret = of_get_phy_mode(np, ðqos->phy_mode);
755 switch (ethqos->phy_mode) {
760 ethqos->configure_func = ethqos_configure_rgmii;
763 ethqos->configure_func = ethqos_configure_sgmii;
767 phy_modes(ethqos->phy_mode));
771 ethqos->pdev = pdev;
772 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
773 if (IS_ERR(ethqos->rgmii_base))
774 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
777 ethqos->mac_base = stmmac_res.addr;
780 ethqos->por = data->por;
781 ethqos->num_por = data->num_por;
782 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
783 ethqos->has_emac_ge_3 = data->has_emac_ge_3;
785 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
786 if (IS_ERR(ethqos->link_clk))
787 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk),
790 ret = ethqos_clks_config(ethqos, true);
794 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
798 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
799 if (IS_ERR(ethqos->serdes_phy))
800 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
803 ethqos->speed = SPEED_1000;
804 ethqos_update_link_clk(ethqos, SPEED_1000);
805 ethqos_set_func_clk_en(ethqos);
807 plat_dat->bsp_priv = ethqos;
812 if (ethqos->has_emac_ge_3)
817 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
824 if (ethqos->serdes_phy) {
833 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
834 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
835 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
836 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
844 .name = "qcom-ethqos",