Lines Matching defs:x
36 #define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) argument
37 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) argument
38 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) argument
39 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) argument
40 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) argument
43 #define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) argument
47 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x) argument
53 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 argument
54 #define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0) argument
56 #define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4)) argument
78 #define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4) argument
84 #define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \ argument
92 #define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x)) argument
94 #define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x)) argument
96 #define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x)) argument
98 #define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x)) argument
100 #define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x)) argument
102 #define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x)) argument
104 #define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x)) argument