Lines Matching refs:netsec_write
331 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) in netsec_write() function
385 netsec_write(priv, MAC_REG_DATA, value); in netsec_mac_write()
386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); in netsec_mac_write()
395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); in netsec_mac_read()
560 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, in netsec_et_set_coalesce()
562 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, in netsec_et_set_coalesce()
564 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); in netsec_et_set_coalesce()
565 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); in netsec_et_set_coalesce()
572 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, in netsec_et_set_coalesce()
574 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, in netsec_et_set_coalesce()
576 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); in netsec_et_set_coalesce()
577 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); in netsec_et_set_coalesce()
776 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts); in netsec_xdp_ring_tx_db()
1092 netsec_write(priv, NETSEC_REG_INTEN_SET, in netsec_napi_poll()
1194 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ in netsec_netdev_start_xmit()
1362 netsec_write(priv, reg, readl(ucode + i * 4)); in netsec_netdev_load_ucode_region()
1408 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, in netsec_reset_hardware()
1410 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, in netsec_reset_hardware()
1422 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); in netsec_reset_hardware()
1423 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); in netsec_reset_hardware()
1424 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); in netsec_reset_hardware()
1430 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, in netsec_reset_hardware()
1432 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, in netsec_reset_hardware()
1435 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, in netsec_reset_hardware()
1437 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, in netsec_reset_hardware()
1441 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, in netsec_reset_hardware()
1443 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, in netsec_reset_hardware()
1457 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); in netsec_reset_hardware()
1458 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); in netsec_reset_hardware()
1468 netsec_write(priv, NETSEC_REG_TOP_STATUS, in netsec_reset_hardware()
1476 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); in netsec_reset_hardware()
1477 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); in netsec_reset_hardware()
1484 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); in netsec_reset_hardware()
1487 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); in netsec_reset_hardware()
1517 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); in netsec_start_gmac()
1521 netsec_write(priv, MAC_REG_DESC_INIT, 1); in netsec_start_gmac()
1548 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); in netsec_start_gmac()
1549 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); in netsec_start_gmac()
1571 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); in netsec_stop_gmac()
1572 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); in netsec_stop_gmac()
1598 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); in netsec_irq_handler()
1602 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); in netsec_irq_handler()
1606 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); in netsec_irq_handler()
1662 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); in netsec_netdev_open()
1684 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); in netsec_netdev_stop()
2174 netsec_write(priv, NETSEC_REG_CLK_EN, 0); in netsec_runtime_suspend()
2187 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | in netsec_runtime_resume()