Lines Matching refs:SMC_REG
478 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
497 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
516 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
533 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
538 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
543 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
569 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
581 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
586 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
587 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
588 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
593 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
598 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
611 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
625 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
630 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
636 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
641 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
644 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
648 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
656 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
661 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
666 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
679 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
680 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
681 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
682 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
687 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
698 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
704 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
711 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
835 #define SMC_REG(lp, reg, bank) \ macro
846 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) macro
867 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
947 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
969 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
987 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \