209 #define sw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
344 	sw32(cr, rfcrSave | RELOAD);  in sis635_get_mac_addr()
345 	sw32(cr, 0);  in sis635_get_mac_addr()
348 	sw32(rfcr, rfcrSave & ~RFEN);  in sis635_get_mac_addr()
352 		sw32(rfcr, (i << RFADDR_shift));  in sis635_get_mac_addr()
358 	sw32(rfcr, rfcrSave | RFEN);  in sis635_get_mac_addr()
387 	sw32(mear, EEREQ);  in sis96x_get_mac_addr()
402 	sw32(mear, EEDONE);  in sis96x_get_mac_addr()
550 		sw32(cr, ACCESSMODE | sr32(cr));  in sis900_probe()
829 	sw32(mear, 0);  in read_eeprom()
831 	sw32(mear, EECS);  in read_eeprom()
838 		sw32(mear, dataval);  in read_eeprom()
840 		sw32(mear, dataval | EECLK);  in read_eeprom()
843 	sw32(mear, EECS);  in read_eeprom()
848 		sw32(mear, EECS);  in read_eeprom()
850 		sw32(mear, EECS | EECLK);  in read_eeprom()
857 	sw32(mear, 0);  in read_eeprom()
872 	sw32(mear, MDIO | MDDIR);  in mdio_idle()
874 	sw32(mear, MDIO | MDDIR | MDC);  in mdio_idle()
884 		sw32(mear, MDDIR | MDIO);  in mdio_reset()
886 		sw32(mear, MDDIR | MDIO | MDC);  in mdio_reset()
916 		sw32(mear, dataval);  in mdio_read()
918 		sw32(mear, dataval | MDC);  in mdio_read()
924 		sw32(mear, 0);  in mdio_read()
927 		sw32(mear, MDC);  in mdio_read()
930 	sw32(mear, 0x00);  in mdio_read()
973 		sw32(mear, dataval);  in mdio_write()
975 		sw32(mear, dataval | MDC);  in mdio_write()
987 	sw32(mear, 0x00);  in mdio_write()
1070 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);  in sis900_open()
1071 	sw32(cr, RxENA | sr32(cr));  in sis900_open()
1072 	sw32(ier, IE);  in sis900_open()
1104 	sw32(rfcr, rfcrSave & ~RFEN);  in sis900_init_rxfilter()
1110 		sw32(rfcr, i << RFADDR_shift);  in sis900_init_rxfilter()
1111 		sw32(rfdr, w);  in sis900_init_rxfilter()
1120 	sw32(rfcr, rfcrSave | RFEN);  in sis900_init_rxfilter()
1150 	sw32(txdp, sis_priv->tx_ring_dma);  in sis900_init_tx_ring()
1211 	sw32(rxdp, sis_priv->rx_ring_dma);  in sis900_init_rx_ring()
1385 		sw32(cfg, ~EXD & sr32(cfg));  in sis900_check_mode()
1389 		sw32(cfg, EXD | sr32(cfg));  in sis900_check_mode()
1443 	sw32(txcfg, tx_flags);  in sis900_set_mode()
1444 	sw32(rxcfg, rx_flags);  in sis900_set_mode()
1562 	sw32(imr, 0x0000);  in sis900_tx_timeout()
1591 	sw32(txdp, sis_priv->tx_ring_dma);  in sis900_tx_timeout()
1594 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);  in sis900_tx_timeout()
1636 	sw32(cr, TxENA | sr32(cr));  in sis900_start_xmit()
1886 	sw32(cr , RxENA | sr32(cr));  in sis900_rx()
1980 	sw32(imr, 0x0000);  in sis900_close()
1981 	sw32(ier, 0x0000);  in sis900_close()
1984 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_close()
2102 		sw32(pmctrl, pmctrl_bits);  in sis900_set_wol()
2117 	sw32(pmctrl, pmctrl_bits);  in sis900_set_wol()
2160 		sw32(mear, EEREQ);  in sis900_read_eeprom()
2171 		sw32(mear, EEDONE);  in sis900_read_eeprom()
2426 		sw32(rfcr, (u32)(0x00000004 + i) << RFADDR_shift);  in set_rx_mode()
2427 		sw32(rfdr, mc_filter[i]);  in set_rx_mode()
2430 	sw32(rfcr, RFEN | rx_mode);  in set_rx_mode()
2438 		sw32(cr, cr_saved | TxDIS | RxDIS);  in set_rx_mode()
2440 		sw32(txcfg, sr32(txcfg) | TxMLB);  in set_rx_mode()
2441 		sw32(rxcfg, sr32(rxcfg) | RxATX);  in set_rx_mode()
2443 		sw32(cr, cr_saved);  in set_rx_mode()
2463 	sw32(ier, 0);  in sis900_reset()
2464 	sw32(imr, 0);  in sis900_reset()
2465 	sw32(rfcr, 0);  in sis900_reset()
2467 	sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));  in sis900_reset()
2475 		sw32(cfg, PESEL | RND_CNT);  in sis900_reset()
2477 		sw32(cfg, PESEL);  in sis900_reset()
2522 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_suspend()
2550 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);  in sis900_resume()
2551 	sw32(cr, RxENA | sr32(cr));  in sis900_resume()
2552 	sw32(ier, IE);  in sis900_resume()