23 	u32 reg_val;  in sxgbe_mtl_init()  local
25 	reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
26 	reg_val &= ETS_RST;  in sxgbe_mtl_init()
31 		reg_val &= ETS_WRR;  in sxgbe_mtl_init()
34 		reg_val |= ETS_WFQ;  in sxgbe_mtl_init()
37 		reg_val |= ETS_DWRR;  in sxgbe_mtl_init()
40 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
44 		reg_val &= RAA_SP;  in sxgbe_mtl_init()
47 		reg_val |= RAA_WSP;  in sxgbe_mtl_init()
50 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
64 	u32 fifo_bits, reg_val;  in sxgbe_mtl_set_txfifosize()  local
68 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_txfifosize()
69 	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);  in sxgbe_mtl_set_txfifosize()
70 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_txfifosize()
76 	u32 fifo_bits, reg_val;  in sxgbe_mtl_set_rxfifosize()  local
80 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_rxfifosize()
81 	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);  in sxgbe_mtl_set_rxfifosize()
82 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_rxfifosize()
87 	u32 reg_val;  in sxgbe_mtl_enable_txqueue()  local
89 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_enable_txqueue()
90 	reg_val |= SXGBE_MTL_ENABLE_QUEUE;  in sxgbe_mtl_enable_txqueue()
91 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_enable_txqueue()
96 	u32 reg_val;  in sxgbe_mtl_disable_txqueue()  local
98 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_disable_txqueue()
99 	reg_val &= ~SXGBE_MTL_ENABLE_QUEUE;  in sxgbe_mtl_disable_txqueue()
100 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_disable_txqueue()
106 	u32 reg_val;  in sxgbe_mtl_fc_active()  local
108 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_active()
109 	reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_ACTIVE);  in sxgbe_mtl_fc_active()
110 	reg_val |= (threshold << RX_FC_ACTIVE);  in sxgbe_mtl_fc_active()
112 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_active()
117 	u32 reg_val;  in sxgbe_mtl_fc_enable()  local
119 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_enable()
120 	reg_val |= SXGBE_MTL_ENABLE_FC;  in sxgbe_mtl_fc_enable()
121 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_enable()
127 	u32 reg_val;  in sxgbe_mtl_fc_deactive()  local
129 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_deactive()
130 	reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_DEACTIVE);  in sxgbe_mtl_fc_deactive()
131 	reg_val |= (threshold << RX_FC_DEACTIVE);  in sxgbe_mtl_fc_deactive()
133 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_deactive()
138 	u32 reg_val;  in sxgbe_mtl_fep_enable()  local
140 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_enable()
141 	reg_val |= SXGBE_MTL_RXQ_OP_FEP;  in sxgbe_mtl_fep_enable()
143 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_enable()
148 	u32 reg_val;  in sxgbe_mtl_fep_disable()  local
150 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_disable()
151 	reg_val &= ~(SXGBE_MTL_RXQ_OP_FEP);  in sxgbe_mtl_fep_disable()
153 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_disable()
158 	u32 reg_val;  in sxgbe_mtl_fup_enable()  local
160 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_enable()
161 	reg_val |= SXGBE_MTL_RXQ_OP_FUP;  in sxgbe_mtl_fup_enable()
163 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_enable()
168 	u32 reg_val;  in sxgbe_mtl_fup_disable()  local
170 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_disable()
171 	reg_val &= ~(SXGBE_MTL_RXQ_OP_FUP);  in sxgbe_mtl_fup_disable()
173 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_disable()
180 	u32 reg_val;  in sxgbe_set_tx_mtl_mode()  local
182 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_set_tx_mtl_mode()
185 		reg_val |= SXGBE_MTL_SFMODE;  in sxgbe_set_tx_mtl_mode()
189 			reg_val |= MTL_CONTROL_TTC_64;  in sxgbe_set_tx_mtl_mode()
191 			reg_val |= MTL_CONTROL_TTC_96;  in sxgbe_set_tx_mtl_mode()
193 			reg_val |= MTL_CONTROL_TTC_128;  in sxgbe_set_tx_mtl_mode()
195 			reg_val |= MTL_CONTROL_TTC_192;  in sxgbe_set_tx_mtl_mode()
197 			reg_val |= MTL_CONTROL_TTC_256;  in sxgbe_set_tx_mtl_mode()
199 			reg_val |= MTL_CONTROL_TTC_384;  in sxgbe_set_tx_mtl_mode()
201 			reg_val |= MTL_CONTROL_TTC_512;  in sxgbe_set_tx_mtl_mode()
205 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_set_tx_mtl_mode()
211 	u32 reg_val;  in sxgbe_set_rx_mtl_mode()  local
213 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_set_rx_mtl_mode()
216 		reg_val |= SXGBE_RX_MTL_SFMODE;  in sxgbe_set_rx_mtl_mode()
219 			reg_val |= MTL_CONTROL_RTC_64;  in sxgbe_set_rx_mtl_mode()
221 			reg_val |= MTL_CONTROL_RTC_96;  in sxgbe_set_rx_mtl_mode()
223 			reg_val |= MTL_CONTROL_RTC_128;  in sxgbe_set_rx_mtl_mode()
227 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_set_rx_mtl_mode()