43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num,  in sxgbe_dma_channel_init()  argument
50 	reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));  in sxgbe_dma_channel_init()
54 		writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));  in sxgbe_dma_channel_init()
56 		reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));  in sxgbe_dma_channel_init()
58 		writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));  in sxgbe_dma_channel_init()
60 		reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));  in sxgbe_dma_channel_init()
62 		writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));  in sxgbe_dma_channel_init()
67 	       ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num));  in sxgbe_dma_channel_init()
69 	       ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num));  in sxgbe_dma_channel_init()
72 	       ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num));  in sxgbe_dma_channel_init()
74 	       ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num));  in sxgbe_dma_channel_init()
82 	       ioaddr + SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num));  in sxgbe_dma_channel_init()
86 	       ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num));  in sxgbe_dma_channel_init()
88 	writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num));  in sxgbe_dma_channel_init()
89 	writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num));  in sxgbe_dma_channel_init()
93 	       ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num));  in sxgbe_dma_channel_init()
96 static void sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num)  in sxgbe_enable_dma_transmission()  argument
100 	tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));  in sxgbe_enable_dma_transmission()
102 	writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));  in sxgbe_enable_dma_transmission()