436 			desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index));  in rswitch_gwca_queue_ext_ts_fill()
981 static int rswitch_etha_change_mode(struct rswitch_etha *etha,  in rswitch_etha_change_mode()  argument
986 	if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index))  in rswitch_etha_change_mode()
987 		rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1);  in rswitch_etha_change_mode()
989 	iowrite32(mode, etha->addr + EAMC);  in rswitch_etha_change_mode()
991 	ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode);  in rswitch_etha_change_mode()
994 		rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0);  in rswitch_etha_change_mode()
999 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha)  in rswitch_etha_read_mac_address()  argument
1001 	u32 mrmac0 = ioread32(etha->addr + MRMAC0);  in rswitch_etha_read_mac_address()
1002 	u32 mrmac1 = ioread32(etha->addr + MRMAC1);  in rswitch_etha_read_mac_address()
1003 	u8 *mac = &etha->mac_addr[0];  in rswitch_etha_read_mac_address()
1013 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac)  in rswitch_etha_write_mac_address()  argument
1015 	iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0);  in rswitch_etha_write_mac_address()
1017 		  etha->addr + MRMAC1);  in rswitch_etha_write_mac_address()
1020 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha)  in rswitch_etha_wait_link_verification()  argument
1022 	iowrite32(MLVC_PLV, etha->addr + MLVC);  in rswitch_etha_wait_link_verification()
1024 	return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0);  in rswitch_etha_wait_link_verification()
1027 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)  in rswitch_rmac_setting()  argument
1031 	rswitch_etha_write_mac_address(etha, mac);  in rswitch_rmac_setting()
1033 	switch (etha->speed) {  in rswitch_rmac_setting()
1047 	iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC);  in rswitch_rmac_setting()
1050 static void rswitch_etha_enable_mii(struct rswitch_etha *etha)  in rswitch_etha_enable_mii()  argument
1052 	rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,  in rswitch_etha_enable_mii()
1053 		       MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06));  in rswitch_etha_enable_mii()
1054 	rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45);  in rswitch_etha_enable_mii()
1057 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)  in rswitch_etha_hw_init()  argument
1061 	err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);  in rswitch_etha_hw_init()
1064 	err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG);  in rswitch_etha_hw_init()
1068 	iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC);  in rswitch_etha_hw_init()
1069 	rswitch_rmac_setting(etha, mac);  in rswitch_etha_hw_init()
1070 	rswitch_etha_enable_mii(etha);  in rswitch_etha_hw_init()
1072 	err = rswitch_etha_wait_link_verification(etha);  in rswitch_etha_hw_init()
1076 	err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);  in rswitch_etha_hw_init()
1080 	return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION);  in rswitch_etha_hw_init()
1083 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read,  in rswitch_etha_set_access()  argument
1093 	writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);  in rswitch_etha_set_access()
1096 	iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);  in rswitch_etha_set_access()
1098 	ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);  in rswitch_etha_set_access()
1102 	rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);  in rswitch_etha_set_access()
1105 		writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);  in rswitch_etha_set_access()
1107 		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);  in rswitch_etha_set_access()
1111 		ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;  in rswitch_etha_set_access()
1113 		rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);  in rswitch_etha_set_access()
1116 			  etha->addr + MPSM);  in rswitch_etha_set_access()
1118 		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS);  in rswitch_etha_set_access()
1127 	struct rswitch_etha *etha = bus->priv;  in rswitch_etha_mii_read_c45()  local
1129 	return rswitch_etha_set_access(etha, true, addr, devad, regad, 0);  in rswitch_etha_mii_read_c45()
1135 	struct rswitch_etha *etha = bus->priv;  in rswitch_etha_mii_write_c45()  local
1137 	return rswitch_etha_set_access(etha, false, addr, devad, regad, val);  in rswitch_etha_mii_write_c45()
1158 		if (index == rdev->etha->index) {  in rswitch_get_port_node()
1179 	err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface);  in rswitch_etha_get_params()
1185 		rdev->etha->speed = max_speed;  in rswitch_etha_get_params()
1190 	switch (rdev->etha->phy_interface) {  in rswitch_etha_get_params()
1192 		rdev->etha->speed = SPEED_100;  in rswitch_etha_get_params()
1195 		rdev->etha->speed = SPEED_1000;  in rswitch_etha_get_params()
1198 		rdev->etha->speed = SPEED_2500;  in rswitch_etha_get_params()
1218 	sprintf(mii_bus->id, "etha%d", rdev->etha->index);  in rswitch_mii_register()
1219 	mii_bus->priv = rdev->etha;  in rswitch_mii_register()
1231 	rdev->etha->mii = mii_bus;  in rswitch_mii_register()
1241 	if (rdev->etha->mii) {  in rswitch_mii_unregister()
1242 		mdiobus_unregister(rdev->etha->mii);  in rswitch_mii_unregister()
1243 		mdiobus_free(rdev->etha->mii);  in rswitch_mii_unregister()
1244 		rdev->etha->mii = NULL;  in rswitch_mii_unregister()
1253 	if (phydev->link != rdev->etha->link) {  in rswitch_adjust_link()
1260 		rdev->etha->link = phydev->link;  in rswitch_adjust_link()
1263 		    phydev->speed != rdev->etha->speed) {  in rswitch_adjust_link()
1264 			rdev->etha->speed = phydev->speed;  in rswitch_adjust_link()
1266 			rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);  in rswitch_adjust_link()
1267 			phy_set_speed(rdev->serdes, rdev->etha->speed);  in rswitch_adjust_link()
1278 	switch (rdev->etha->speed) {  in rswitch_phy_remove_link_mode()
1295 	phy_set_max_speed(phydev, rdev->etha->speed);  in rswitch_phy_remove_link_mode()
1317 	__set_bit(rdev->etha->phy_interface, phydev->host_interfaces);  in rswitch_phy_device_init()
1320 				rdev->etha->phy_interface);  in rswitch_phy_device_init()
1351 			       rdev->etha->phy_interface);  in rswitch_serdes_set_params()
1355 	return phy_set_speed(rdev->serdes, rdev->etha->speed);  in rswitch_serdes_set_params()
1362 	if (!rdev->etha->operated) {  in rswitch_ether_port_init_one()
1363 		err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);  in rswitch_ether_port_init_one()
1367 			rdev->etha->operated = true;  in rswitch_ether_port_init_one()
1525 	desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) |  in rswitch_start_xmit()
1695 	struct rswitch_etha *etha = &priv->etha[index];  in rswitch_etha_init()  local
1697 	memset(etha, 0, sizeof(*etha));  in rswitch_etha_init()
1698 	etha->index = index;  in rswitch_etha_init()
1699 	etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE;  in rswitch_etha_init()
1700 	etha->coma_addr = priv->addr;  in rswitch_etha_init()
1706 	etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1;  in rswitch_etha_init()
1731 	rdev->etha = &priv->etha[index];  in rswitch_device_alloc()
1746 		if (is_valid_ether_addr(rdev->etha->mac_addr))  in rswitch_device_alloc()
1747 			eth_hw_addr_set(ndev, rdev->etha->mac_addr);  in rswitch_device_alloc()
1756 	if (rdev->priv->gwca.speed < rdev->etha->speed)  in rswitch_device_alloc()
1757 		rdev->priv->gwca.speed = rdev->etha->speed;  in rswitch_device_alloc()
1800 		rswitch_etha_read_mac_address(&priv->etha[i]);  in rswitch_init()