Lines Matching refs:RTL_W32
82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) macro
844 RTL_W32(tp, ERIDR, val); in _rtl_eri_write()
846 RTL_W32(tp, ERIAR, cmd); in _rtl_eri_write()
862 RTL_W32(tp, ERIAR, cmd); in _rtl_eri_read()
905 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); in r8168_phy_ocp_write()
915 RTL_W32(tp, GPHY_OCP, reg << 15); in r8168_phy_ocp_read()
926 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); in __r8168_mac_ocp_write()
943 RTL_W32(tp, OCPDR, reg << 15); in __r8168_mac_ocp_read()
1038 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
1052 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
1075 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1080 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1145 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | in rtl_ephy_write()
1155 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); in rtl_ephy_read()
1163 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1176 RTL_W32(tp, OCPDR, data); in r8168dp_ocp_write()
1177 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1364 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); in rtl8168d_efuse_read()
1381 RTL_W32(tp, IntrStatus_8125, bits); in rtl_ack_events()
1389 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1397 RTL_W32(tp, IntrMask_8125, tp->irq_mask); in rtl_irq_enable()
1591 RTL_W32(tp, RxConfig, rx_config); in rtl_set_rx_config_features()
1680 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); in rtl8169_do_counters()
1682 RTL_W32(tp, CounterAddrLow, cmd); in rtl8169_do_counters()
1683 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); in rtl8169_do_counters()
2319 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); in rtl_rar_set()
2322 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); in rtl_rar_set()
2350 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); in rtl_init_rxcfg()
2355 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); in rtl_init_rxcfg()
2358 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); in rtl_init_rxcfg()
2361 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); in rtl_init_rxcfg()
2364 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | in rtl_init_rxcfg()
2368 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); in rtl_init_rxcfg()
2516 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); in rtl_rx_close()
2562 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_disable_rxdvgate()
2567 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); in rtl_enable_rxdvgate()
2575 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | in rtl_wol_enable_rx()
2605 RTL_W32(tp, TxConfig, val); in rtl_set_tx_config_registers()
2621 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
2622 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
2623 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
2624 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
2641 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2678 RTL_W32(tp, MAR0 + 4, mc_filter[1]); in rtl_set_rx_mode()
2679 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2682 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); in rtl_set_rx_mode()
2694 RTL_W32(tp, CSIDR, value); in rtl_csi_write()
2695 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | in rtl_csi_write()
2705 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | in rtl_csi_read()
3011 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); in rtl_hw_start_8168e_1()
3012 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); in rtl_hw_start_8168e_1()
3046 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168e_2()
3067 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168f()
3555 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3558 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3584 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3605 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3607 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); in rtl_hw_start_8106()
3781 RTL_W32(tp, i, 0); in rtl_hw_start_8125()