Lines Matching +full:0 +full:x8c20
64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75 #define OCP_STD_PHY_BASE 0xa400
146 { PCI_VDEVICE(REALTEK, 0x2502) },
147 { PCI_VDEVICE(REALTEK, 0x2600) },
148 { PCI_VDEVICE(REALTEK, 0x8129) },
149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
150 { PCI_VDEVICE(REALTEK, 0x8161) },
151 { PCI_VDEVICE(REALTEK, 0x8162) },
152 { PCI_VDEVICE(REALTEK, 0x8167) },
153 { PCI_VDEVICE(REALTEK, 0x8168) },
154 { PCI_VDEVICE(NCUBE, 0x8168) },
155 { PCI_VDEVICE(REALTEK, 0x8169) },
156 { PCI_VENDOR_ID_DLINK, 0x4300,
157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
158 { PCI_VDEVICE(DLINK, 0x4300) },
159 { PCI_VDEVICE(DLINK, 0x4302) },
160 { PCI_VDEVICE(AT, 0xc107) },
161 { PCI_VDEVICE(USR, 0x0116) },
162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
164 { PCI_VDEVICE(REALTEK, 0x8125) },
165 { PCI_VDEVICE(REALTEK, 0x3000) },
172 MAC0 = 0, /* Ethernet hardware address. */
175 CounterAddrLow = 0x10,
176 CounterAddrHigh = 0x14,
177 TxDescStartAddrLow = 0x20,
178 TxDescStartAddrHigh = 0x24,
179 TxHDescStartAddrLow = 0x28,
180 TxHDescStartAddrHigh = 0x2c,
181 FLASH = 0x30,
182 ERSR = 0x36,
183 ChipCmd = 0x37,
184 TxPoll = 0x38,
185 IntrMask = 0x3c,
186 IntrStatus = 0x3e,
188 TxConfig = 0x40,
192 RxConfig = 0x44,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
210 Config3 = 0x54,
211 Config4 = 0x55,
212 Config5 = 0x56,
213 PHYAR = 0x60,
214 PHYstatus = 0x6c,
215 RxMaxSize = 0xda,
216 CPlusCmd = 0xe0,
217 IntrMitigate = 0xe2,
222 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
224 #define RTL_COALESCE_T_MAX 0x0fU
227 RxDescAddrLow = 0xe4,
228 RxDescAddrHigh = 0xe8,
229 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
231 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
233 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
236 #define EarlySize 0x27
238 FuncEvent = 0xf0,
239 FuncEventMask = 0xf4,
240 FuncPresetState = 0xf8,
241 IBCR0 = 0xf8,
242 IBCR2 = 0xf9,
243 IBIMR0 = 0xfa,
244 IBISR0 = 0xfb,
245 FuncForceEvent = 0xfc,
249 CSIDR = 0x64,
250 CSIAR = 0x68,
251 #define CSIAR_FLAG 0x80000000
252 #define CSIAR_WRITE_CMD 0x80000000
253 #define CSIAR_BYTE_ENABLE 0x0000f000
254 #define CSIAR_ADDR_MASK 0x00000fff
255 PMCH = 0x6f,
259 EPHYAR = 0x80,
260 #define EPHYAR_FLAG 0x80000000
261 #define EPHYAR_WRITE_CMD 0x80000000
262 #define EPHYAR_REG_MASK 0x1f
264 #define EPHYAR_DATA_MASK 0xffff
265 DLLPR = 0xd0,
268 DBG_REG = 0xd1,
271 TWSI = 0xd2,
272 MCU = 0xd3,
280 EFUSEAR = 0xdc,
281 #define EFUSEAR_FLAG 0x80000000
282 #define EFUSEAR_WRITE_CMD 0x80000000
283 #define EFUSEAR_READ_CMD 0x00000000
284 #define EFUSEAR_REG_MASK 0x03ff
286 #define EFUSEAR_DATA_MASK 0xff
287 MISC_1 = 0xf2,
292 LED_FREQ = 0x1a,
293 EEE_LED = 0x1b,
294 ERIDR = 0x70,
295 ERIAR = 0x74,
296 #define ERIAR_FLAG 0x80000000
297 #define ERIAR_WRITE_CMD 0x80000000
298 #define ERIAR_READ_CMD 0x00000000
301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
311 EPHY_RXER_NUM = 0x7c,
312 OCPDR = 0xb0, /* OCP GPHY access */
313 #define OCPDR_WRITE_CMD 0x80000000
314 #define OCPDR_READ_CMD 0x00000000
315 #define OCPDR_REG_MASK 0x7f
317 #define OCPDR_DATA_MASK 0xffff
318 OCPAR = 0xb4,
319 #define OCPAR_FLAG 0x80000000
320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
321 #define OCPAR_GPHY_READ_CMD 0x0000f060
322 GPHY_OCP = 0xb8,
323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
324 MISC = 0xf0, /* 8168e only. */
333 IntrMask_8125 = 0x38,
334 IntrStatus_8125 = 0x3c,
335 TxPoll_8125 = 0x90,
336 MAC0_BKP = 0x19e0,
337 EEE_TXIDLE_TIMER_8125 = 0x6048,
348 SYSErr = 0x8000,
349 PCSTimeout = 0x4000,
350 SWInt = 0x0100,
351 TxDescUnavail = 0x0080,
352 RxFIFOOver = 0x0040,
353 LinkChg = 0x0020,
354 RxOverflow = 0x0010,
355 TxErr = 0x0008,
356 TxOK = 0x0004,
357 RxErr = 0x0002,
358 RxOK = 0x0001,
367 StopReq = 0x80,
368 CmdReset = 0x10,
369 CmdRxEnb = 0x08,
370 CmdTxEnb = 0x04,
371 RxBufEmpty = 0x01,
374 HPQ = 0x80, /* Poll cmd on the high prio queue */
375 NPQ = 0x40, /* Poll cmd on the low prio queue */
376 FSWInt = 0x01, /* Forced software interrupt */
379 Cfg9346_Lock = 0x00,
380 Cfg9346_Unlock = 0xc0,
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
386 AcceptBroadcast = 0x08,
387 AcceptMulticast = 0x04,
388 AcceptMyPhys = 0x02,
389 AcceptAllPhys = 0x01,
390 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
391 #define RX_CONFIG_ACCEPT_MASK 0x3f
395 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
404 PMEnable = (1 << 0), /* Power Management Enable */
409 PCI_Clock_66MHz = 0x01,
410 PCI_Clock_33MHz = 0x00,
417 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
428 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
429 ASPM_en = (1 << 0), /* ASPM enable */
442 Mac_dbgo_sel = 0x001c, // 8168
447 #define INTT_MASK GENMASK(1, 0)
451 TBI_Enable = 0x80,
452 TxFlowCtrl = 0x40,
453 RxFlowCtrl = 0x20,
454 _1000bpsF = 0x10,
455 _100bps = 0x08,
456 _10bps = 0x04,
457 LinkStatus = 0x02,
458 FullDup = 0x01,
461 CounterReset = 0x1,
464 CounterDump = 0x8,
482 #define TD_MSS_MAX 0x07ffu /* MSS value */
503 #define GTTCPHO_MAX 0x7f
507 #define TCPHO_MAX 0x3ff
518 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
608 RTL_FLAG_TASK_ENABLED = 0,
772 for (i = 0; i < ETH_ALEN; i++) in rtl_read_mac_from_reg()
786 for (i = 0; i < n; i++) { in rtl_loop_wait()
828 *cmd |= 0xf70 << 18; in r8168fp_adjust_ocp_cmd()
841 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) in _rtl_eri_write()
865 RTL_R32(tp, ERIDR) : ~0; in _rtl_eri_read()
882 rtl_w0w1_eri(tp, addr, p, 0); in rtl_eri_set_bits()
887 rtl_w0w1_eri(tp, addr, 0, m); in rtl_eri_clear_bits()
892 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); in rtl_ocp_reg_failure()
913 return 0; in r8168_phy_ocp_read()
918 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; in r8168_phy_ocp_read()
941 return 0; in __r8168_mac_ocp_read()
980 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
982 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
991 if (reg == 0x1f) { in r8168g_mdio_write()
997 reg -= 0x10; in r8168g_mdio_write()
1007 if (reg == 0x1f) in r8168g_mdio_read()
1008 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; in r8168g_mdio_read()
1011 reg -= 0x10; in r8168g_mdio_read()
1018 if (reg == 0x1f) { in mac_mcu_write()
1033 return RTL_R32(tp, PHYAR) & 0x80000000; in DECLARE_RTL_COND()
1038 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
1052 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
1055 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; in r8169_mdio_read()
1071 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1075 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1080 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1098 return 0xc912; in r8168dp_2_mdio_read()
1158 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; in rtl_ephy_read()
1163 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1165 RTL_R32(tp, OCPDR) : ~0; in r8168dp_ocp_read()
1177 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1184 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, in r8168ep_ocp_write()
1190 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); in r8168dp_oob_notify()
1192 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); in r8168dp_oob_notify()
1195 #define OOB_CMD_RESET 0x00
1196 #define OOB_CMD_DRIVER_START 0x05
1197 #define OOB_CMD_DRIVER_STOP 0x06
1201 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
1210 return r8168dp_ocp_read(tp, reg) & 0x00000800; in DECLARE_RTL_COND()
1215 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; in DECLARE_RTL_COND()
1220 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1225 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1227 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1228 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1262 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); in rtl8168ep_driver_start()
1263 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_start()
1284 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); in rtl8168ep_driver_stop()
1285 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_stop()
1306 return r8168ep_ocp_read(tp, 0x128) & BIT(0); in r8168ep_check_dash()
1353 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1354 rtl_eri_set_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1367 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; in rtl8168d_efuse_read()
1389 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1391 RTL_W16(tp, IntrMask, 0); in rtl_irq_disable()
1405 rtl_ack_events(tp, 0xffffffff); in rtl8169_irq_mask_and_ack()
1416 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1417 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1419 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1420 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1422 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1423 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1430 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1432 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1437 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); in rtl_link_chg_patch()
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); in rtl_link_chg_patch()
1440 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_link_chg_patch()
1478 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1480 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1484 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); in __rtl8169_set_wol()
1486 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); in __rtl8169_set_wol()
1490 for (i = 0; i < tmp; i++) { in __rtl8169_set_wol()
1509 rtl_mod_config2(tp, 0, PME_SIGNAL); in __rtl8169_set_wol()
1511 rtl_mod_config2(tp, PME_SIGNAL, 0); in __rtl8169_set_wol()
1523 tp->dev->wol_enabled = wolopts ? 1 : 0; in __rtl8169_set_wol()
1537 return 0; in rtl8169_set_wol()
1616 return 0; in rtl8169_set_features()
1622 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; in rtl8169_tx_vlan_tag()
1630 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); in rtl8169_rx_vlan_tag()
1641 for (i = 0; i < R8169_REGS_SIZE; i += 4) in rtl8169_get_regs()
1694 * is disabled. If 0xff chip may be in a PCI power-save state. in rtl8169_update_counters()
1696 if (val & CmdRxEnb && val != 0xff) in rtl8169_update_counters()
1744 data[0] = le64_to_cpu(counters->tx_packets); in rtl8169_get_ethtool_stats()
1771 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1779 * (0xe0) bit 1 and bit 0.
1782 * bit[1:0] \ speed 1000M 100M 10M
1783 * 0 0 320ns 2.56us 40.96us
1784 * 0 1 2.56us 20.48us 327.7us
1785 * 1 0 5.12us 40.96us 655.4us
1789 * bit[1:0] \ speed 1000M 100M 10M
1790 * 0 0 5us 2.56us 40.96us
1791 * 0 1 40us 20.48us 327.7us
1792 * 1 0 80us 40.96us 655.4us
1796 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1809 { 0 },
1816 { 0 },
1856 memset(ec, 0, sizeof(*ec)); in rtl_get_coalesce()
1858 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ in rtl_get_coalesce()
1871 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ in rtl_get_coalesce()
1880 return 0; in rtl_get_coalesce()
1883 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1894 for (i = 0; i < 4; i++) { in rtl_coalesce_choose_scale()
1913 u16 w = 0, cp01 = 0; in rtl_set_coalesce()
1924 if (scale < 0) in rtl_set_coalesce()
1928 * not only when usecs=0 because of e.g. the following scenario: in rtl_set_coalesce()
1930 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) in rtl_set_coalesce()
1931 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 in rtl_set_coalesce()
1935 * if we want to ignore rx_frames then it has to be set to 0. in rtl_set_coalesce()
1938 rx_fr = 0; in rtl_set_coalesce()
1940 tx_fr = 0; in rtl_set_coalesce()
1970 return 0; in rtl_set_coalesce()
2019 data->tx_pause = tx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2020 data->rx_pause = rx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2033 return 0; in rtl8169_set_pauseparam()
2067 if (tp->eee_adv >= 0) in rtl_enable_eee()
2072 if (adv >= 0) in rtl_enable_eee()
2083 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be in rtl8169_get_mac_version()
2087 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec in rtl8169_get_mac_version()
2095 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, in rtl8169_get_mac_version()
2098 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2100 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, in rtl8169_get_mac_version()
2101 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2105 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, in rtl8169_get_mac_version()
2106 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, in rtl8169_get_mac_version()
2109 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, in rtl8169_get_mac_version()
2112 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, in rtl8169_get_mac_version()
2113 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, in rtl8169_get_mac_version()
2117 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, in rtl8169_get_mac_version()
2120 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, in rtl8169_get_mac_version()
2124 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, in rtl8169_get_mac_version()
2125 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, in rtl8169_get_mac_version()
2128 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, in rtl8169_get_mac_version()
2130 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, in rtl8169_get_mac_version()
2133 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, in rtl8169_get_mac_version()
2134 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, in rtl8169_get_mac_version()
2135 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, in rtl8169_get_mac_version()
2138 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, in rtl8169_get_mac_version()
2139 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, in rtl8169_get_mac_version()
2140 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, in rtl8169_get_mac_version()
2143 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, in rtl8169_get_mac_version()
2144 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, in rtl8169_get_mac_version()
2149 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, in rtl8169_get_mac_version()
2151 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, in rtl8169_get_mac_version()
2152 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, in rtl8169_get_mac_version()
2155 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, in rtl8169_get_mac_version()
2156 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, in rtl8169_get_mac_version()
2157 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, in rtl8169_get_mac_version()
2158 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, in rtl8169_get_mac_version()
2159 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, in rtl8169_get_mac_version()
2160 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, in rtl8169_get_mac_version()
2161 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, in rtl8169_get_mac_version()
2164 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, in rtl8169_get_mac_version()
2165 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, in rtl8169_get_mac_version()
2168 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, in rtl8169_get_mac_version()
2169 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, in rtl8169_get_mac_version()
2170 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, in rtl8169_get_mac_version()
2171 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
2172 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2173 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2174 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2175 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2176 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, in rtl8169_get_mac_version()
2177 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2178 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2179 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, in rtl8169_get_mac_version()
2182 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, in rtl8169_get_mac_version()
2183 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, in rtl8169_get_mac_version()
2184 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, in rtl8169_get_mac_version()
2185 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, in rtl8169_get_mac_version()
2186 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, in rtl8169_get_mac_version()
2189 { 0x000, 0x000, RTL_GIGA_MAC_NONE } in rtl8169_get_mac_version()
2238 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2240 rtl_eri_set_bits(tp, 0x1b0, 0x0003); in rtl8168_config_eee_mac()
2245 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125a_config_eee_mac()
2246 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); in rtl8125a_config_eee_mac()
2251 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); in rtl8125_set_eee_txidle_timer()
2257 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125b_config_eee_mac()
2262 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); in rtl_rar_exgmac_set()
2263 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); in rtl_rar_exgmac_set()
2264 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); in rtl_rar_exgmac_set()
2265 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); in rtl_rar_exgmac_set()
2272 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); in rtl8168h_2_get_adc_bias_ioffset()
2273 data1 = r8168_mac_ocp_read(tp, 0xdd02); in rtl8168h_2_get_adc_bias_ioffset()
2274 data2 = r8168_mac_ocp_read(tp, 0xdd00); in rtl8168h_2_get_adc_bias_ioffset()
2276 ioffset = (data2 >> 1) & 0x7ff8; in rtl8168h_2_get_adc_bias_ioffset()
2277 ioffset |= data2 & 0x0007; in rtl8168h_2_get_adc_bias_ioffset()
2295 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
2296 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
2297 /* set undocumented MAC Reg C+CR Offset 0x82h */ in rtl8169_init_phy()
2298 RTL_W8(tp, 0x82, 0x01); in rtl8169_init_phy()
2303 tp->pci_dev->subsystem_device == 0xe000) in rtl8169_init_phy()
2304 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); in rtl8169_init_phy()
2342 return 0; in rtl_set_mac_address()
2375 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
2402 RTL_W8(tp, MaxTxPacketSize, 0x24); in r8168e_hw_jumbo_enable()
2404 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); in r8168e_hw_jumbo_enable()
2409 RTL_W8(tp, MaxTxPacketSize, 0x3f); in r8168e_hw_jumbo_disable()
2411 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); in r8168e_hw_jumbo_disable()
2416 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
2421 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
2537 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; in DECLARE_RTL_COND()
2589 rtl_ephy_write(tp, 0x19, 0xff64); in rtl_prepare_power_down()
2632 val = 0x000fff00; in rtl8169_set_magic_reg()
2634 val = 0x00ffff00; in rtl8169_set_magic_reg()
2639 val |= 0xff; in rtl8169_set_magic_reg()
2641 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2648 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; in rtl_set_rx_mode()
2665 mc_filter[1] = mc_filter[0] = 0; in rtl_set_rx_mode()
2672 tmp = mc_filter[0]; in rtl_set_rx_mode()
2673 mc_filter[0] = swab32(mc_filter[1]); in rtl_set_rx_mode()
2679 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2709 RTL_R32(tp, CSIDR) : ~0; in rtl_csi_read()
2717 /* According to Realtek the value at config space address 0x070f in rtl_set_aspm_entry_latency()
2720 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) in rtl_set_aspm_entry_latency()
2721 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us in rtl_set_aspm_entry_latency()
2723 if (pdev->cfg_size > 0x070f && in rtl_set_aspm_entry_latency()
2724 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) in rtl_set_aspm_entry_latency()
2729 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; in rtl_set_aspm_entry_latency()
2730 rtl_csi_write(tp, 0x070c, csi | val << 24); in rtl_set_aspm_entry_latency()
2736 rtl_set_aspm_entry_latency(tp, 0x27); in rtl_set_def_aspm_entry_latency()
2750 while (len-- > 0) { in __rtl_ephy_init()
2789 rtl_eri_set_bits(tp, 0xd4, 0x1f00); in rtl_enable_exit_l1()
2792 rtl_eri_set_bits(tp, 0xd4, 0x0c00); in rtl_enable_exit_l1()
2795 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); in rtl_enable_exit_l1()
2806 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); in rtl_disable_exit_l1()
2809 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); in rtl_disable_exit_l1()
2830 rtl_mod_config5(tp, 0, ASPM_en); in rtl_hw_aspm_clkreq_enable()
2831 rtl_mod_config2(tp, 0, ClkReqEn); in rtl_hw_aspm_clkreq_enable()
2837 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); in rtl_hw_aspm_clkreq_enable()
2839 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); in rtl_hw_aspm_clkreq_enable()
2848 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); in rtl_hw_aspm_clkreq_enable()
2854 rtl_mod_config2(tp, ClkReqEn, 0); in rtl_hw_aspm_clkreq_enable()
2855 rtl_mod_config5(tp, ASPM_en, 0); in rtl_hw_aspm_clkreq_enable()
2865 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); in rtl_set_fifo_size()
2866 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); in rtl_set_fifo_size()
2873 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); in rtl8168g_set_pause_thresholds()
2874 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); in rtl8168g_set_pause_thresholds()
2894 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168cp_1()
2895 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168cp_1()
2896 { 0x03, 0, 0x0042 }, in rtl_hw_start_8168cp_1()
2897 { 0x06, 0x0080, 0x0000 }, in rtl_hw_start_8168cp_1()
2898 { 0x07, 0, 0x2000 } in rtl_hw_start_8168cp_1()
2922 RTL_W8(tp, DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
2928 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168c_1()
2929 { 0x03, 0, 0x0002 }, in rtl_hw_start_8168c_1()
2930 { 0x06, 0x0080, 0x0000 } in rtl_hw_start_8168c_1()
2935 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
2945 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168c_2()
2946 { 0x03, 0x0400, 0x0020 } in rtl_hw_start_8168c_2()
2973 { 0x0b, 0x0000, 0x0048 }, in rtl_hw_start_8168d_4()
2974 { 0x19, 0x0020, 0x0050 }, in rtl_hw_start_8168d_4()
2975 { 0x0c, 0x0100, 0x0020 }, in rtl_hw_start_8168d_4()
2976 { 0x10, 0x0004, 0x0000 }, in rtl_hw_start_8168d_4()
2989 { 0x00, 0x0200, 0x0100 }, in rtl_hw_start_8168e_1()
2990 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_1()
2991 { 0x06, 0x0002, 0x0001 }, in rtl_hw_start_8168e_1()
2992 { 0x06, 0x0000, 0x0030 }, in rtl_hw_start_8168e_1()
2993 { 0x07, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
2994 { 0x00, 0x0000, 0x0020 }, in rtl_hw_start_8168e_1()
2995 { 0x03, 0x5800, 0x2000 }, in rtl_hw_start_8168e_1()
2996 { 0x03, 0x0000, 0x0001 }, in rtl_hw_start_8168e_1()
2997 { 0x01, 0x0800, 0x1000 }, in rtl_hw_start_8168e_1()
2998 { 0x07, 0x0000, 0x4000 }, in rtl_hw_start_8168e_1()
2999 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3000 { 0x19, 0xffff, 0xfe6c }, in rtl_hw_start_8168e_1()
3001 { 0x0a, 0x0000, 0x0040 } in rtl_hw_start_8168e_1()
3014 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_1()
3020 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168e_2()
3021 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168e_2()
3022 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_2()
3023 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168e_2()
3030 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168e_2()
3031 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168e_2()
3032 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168e_2()
3033 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); in rtl_hw_start_8168e_2()
3035 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168e_2()
3036 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168e_2()
3037 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); in rtl_hw_start_8168e_2()
3047 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_2()
3054 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168f()
3055 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168f()
3056 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168f()
3058 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168f()
3059 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); in rtl_hw_start_8168f()
3060 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168f()
3061 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); in rtl_hw_start_8168f()
3068 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168f()
3076 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8168f_1()
3077 { 0x08, 0x0001, 0x0002 }, in rtl_hw_start_8168f_1()
3078 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168f_1()
3079 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168f_1()
3080 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8168f_1()
3081 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168f_1()
3092 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8411()
3093 { 0x0f, 0xffff, 0x5200 }, in rtl_hw_start_8411()
3094 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8411()
3095 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8411()
3096 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8411()
3107 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168g()
3108 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168g()
3113 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); in rtl_hw_start_8168g()
3117 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3118 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3122 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168g()
3123 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168g()
3131 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_1()
3132 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_1()
3133 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8168g_1()
3134 { 0x19, 0x8000, 0x0000 } in rtl_hw_start_8168g_1()
3144 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_2()
3145 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_2()
3146 { 0x19, 0xffff, 0x7c00 }, in rtl_hw_start_8168g_2()
3147 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8168g_2()
3148 { 0x0d, 0xffff, 0x1666 }, in rtl_hw_start_8168g_2()
3149 { 0x00, 0xffff, 0x10a3 }, in rtl_hw_start_8168g_2()
3150 { 0x06, 0xffff, 0xf050 }, in rtl_hw_start_8168g_2()
3151 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8168g_2()
3152 { 0x1d, 0x4000, 0x0000 }, in rtl_hw_start_8168g_2()
3162 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8411_2()
3163 { 0x0c, 0x37d0, 0x0820 }, in rtl_hw_start_8411_2()
3164 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8411_2()
3165 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8411_2()
3166 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8411_2()
3167 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8411_2()
3168 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8411_2()
3169 { 0x06, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3170 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3171 { 0x1d, 0x0000, 0x4000 }, in rtl_hw_start_8411_2()
3181 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); in rtl_hw_start_8411_2()
3182 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); in rtl_hw_start_8411_2()
3183 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); in rtl_hw_start_8411_2()
3184 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); in rtl_hw_start_8411_2()
3185 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); in rtl_hw_start_8411_2()
3186 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); in rtl_hw_start_8411_2()
3187 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); in rtl_hw_start_8411_2()
3188 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); in rtl_hw_start_8411_2()
3190 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); in rtl_hw_start_8411_2()
3192 r8168_mac_ocp_write(tp, 0xF800, 0xE008); in rtl_hw_start_8411_2()
3193 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); in rtl_hw_start_8411_2()
3194 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); in rtl_hw_start_8411_2()
3195 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); in rtl_hw_start_8411_2()
3196 r8168_mac_ocp_write(tp, 0xF808, 0xE027); in rtl_hw_start_8411_2()
3197 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); in rtl_hw_start_8411_2()
3198 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); in rtl_hw_start_8411_2()
3199 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); in rtl_hw_start_8411_2()
3200 r8168_mac_ocp_write(tp, 0xF810, 0xC602); in rtl_hw_start_8411_2()
3201 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); in rtl_hw_start_8411_2()
3202 r8168_mac_ocp_write(tp, 0xF814, 0x0000); in rtl_hw_start_8411_2()
3203 r8168_mac_ocp_write(tp, 0xF816, 0xC502); in rtl_hw_start_8411_2()
3204 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); in rtl_hw_start_8411_2()
3205 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); in rtl_hw_start_8411_2()
3206 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); in rtl_hw_start_8411_2()
3207 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); in rtl_hw_start_8411_2()
3208 r8168_mac_ocp_write(tp, 0xF820, 0x080A); in rtl_hw_start_8411_2()
3209 r8168_mac_ocp_write(tp, 0xF822, 0x6420); in rtl_hw_start_8411_2()
3210 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); in rtl_hw_start_8411_2()
3211 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); in rtl_hw_start_8411_2()
3212 r8168_mac_ocp_write(tp, 0xF828, 0xC516); in rtl_hw_start_8411_2()
3213 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); in rtl_hw_start_8411_2()
3214 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); in rtl_hw_start_8411_2()
3215 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); in rtl_hw_start_8411_2()
3216 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); in rtl_hw_start_8411_2()
3217 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); in rtl_hw_start_8411_2()
3218 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); in rtl_hw_start_8411_2()
3219 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); in rtl_hw_start_8411_2()
3220 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); in rtl_hw_start_8411_2()
3221 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); in rtl_hw_start_8411_2()
3222 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); in rtl_hw_start_8411_2()
3223 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); in rtl_hw_start_8411_2()
3224 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); in rtl_hw_start_8411_2()
3225 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); in rtl_hw_start_8411_2()
3226 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); in rtl_hw_start_8411_2()
3227 r8168_mac_ocp_write(tp, 0xF846, 0xC404); in rtl_hw_start_8411_2()
3228 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); in rtl_hw_start_8411_2()
3229 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); in rtl_hw_start_8411_2()
3230 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); in rtl_hw_start_8411_2()
3231 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); in rtl_hw_start_8411_2()
3232 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); in rtl_hw_start_8411_2()
3233 r8168_mac_ocp_write(tp, 0xF852, 0xE434); in rtl_hw_start_8411_2()
3234 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); in rtl_hw_start_8411_2()
3235 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); in rtl_hw_start_8411_2()
3236 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); in rtl_hw_start_8411_2()
3237 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); in rtl_hw_start_8411_2()
3238 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); in rtl_hw_start_8411_2()
3239 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); in rtl_hw_start_8411_2()
3240 r8168_mac_ocp_write(tp, 0xF860, 0xF007); in rtl_hw_start_8411_2()
3241 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); in rtl_hw_start_8411_2()
3242 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); in rtl_hw_start_8411_2()
3243 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); in rtl_hw_start_8411_2()
3244 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); in rtl_hw_start_8411_2()
3245 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); in rtl_hw_start_8411_2()
3246 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); in rtl_hw_start_8411_2()
3247 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); in rtl_hw_start_8411_2()
3248 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); in rtl_hw_start_8411_2()
3249 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); in rtl_hw_start_8411_2()
3250 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); in rtl_hw_start_8411_2()
3251 r8168_mac_ocp_write(tp, 0xF876, 0xC516); in rtl_hw_start_8411_2()
3252 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); in rtl_hw_start_8411_2()
3253 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); in rtl_hw_start_8411_2()
3254 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); in rtl_hw_start_8411_2()
3255 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); in rtl_hw_start_8411_2()
3256 r8168_mac_ocp_write(tp, 0xF880, 0xC512); in rtl_hw_start_8411_2()
3257 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); in rtl_hw_start_8411_2()
3258 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); in rtl_hw_start_8411_2()
3259 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); in rtl_hw_start_8411_2()
3260 r8168_mac_ocp_write(tp, 0xF888, 0x483F); in rtl_hw_start_8411_2()
3261 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); in rtl_hw_start_8411_2()
3262 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); in rtl_hw_start_8411_2()
3263 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); in rtl_hw_start_8411_2()
3264 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); in rtl_hw_start_8411_2()
3265 r8168_mac_ocp_write(tp, 0xF892, 0xC505); in rtl_hw_start_8411_2()
3266 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); in rtl_hw_start_8411_2()
3267 r8168_mac_ocp_write(tp, 0xF896, 0xC502); in rtl_hw_start_8411_2()
3268 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); in rtl_hw_start_8411_2()
3269 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); in rtl_hw_start_8411_2()
3270 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); in rtl_hw_start_8411_2()
3271 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); in rtl_hw_start_8411_2()
3272 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); in rtl_hw_start_8411_2()
3273 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); in rtl_hw_start_8411_2()
3274 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); in rtl_hw_start_8411_2()
3275 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); in rtl_hw_start_8411_2()
3276 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); in rtl_hw_start_8411_2()
3277 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); in rtl_hw_start_8411_2()
3278 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); in rtl_hw_start_8411_2()
3279 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); in rtl_hw_start_8411_2()
3280 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); in rtl_hw_start_8411_2()
3281 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); in rtl_hw_start_8411_2()
3282 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); in rtl_hw_start_8411_2()
3283 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); in rtl_hw_start_8411_2()
3284 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); in rtl_hw_start_8411_2()
3285 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); in rtl_hw_start_8411_2()
3286 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); in rtl_hw_start_8411_2()
3287 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); in rtl_hw_start_8411_2()
3288 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); in rtl_hw_start_8411_2()
3289 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); in rtl_hw_start_8411_2()
3290 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); in rtl_hw_start_8411_2()
3291 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); in rtl_hw_start_8411_2()
3292 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); in rtl_hw_start_8411_2()
3293 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); in rtl_hw_start_8411_2()
3294 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); in rtl_hw_start_8411_2()
3295 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); in rtl_hw_start_8411_2()
3296 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); in rtl_hw_start_8411_2()
3297 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); in rtl_hw_start_8411_2()
3298 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); in rtl_hw_start_8411_2()
3299 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); in rtl_hw_start_8411_2()
3300 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); in rtl_hw_start_8411_2()
3301 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); in rtl_hw_start_8411_2()
3302 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); in rtl_hw_start_8411_2()
3304 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); in rtl_hw_start_8411_2()
3306 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); in rtl_hw_start_8411_2()
3307 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); in rtl_hw_start_8411_2()
3308 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); in rtl_hw_start_8411_2()
3309 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); in rtl_hw_start_8411_2()
3310 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); in rtl_hw_start_8411_2()
3311 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); in rtl_hw_start_8411_2()
3312 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); in rtl_hw_start_8411_2()
3318 { 0x1e, 0x0800, 0x0001 }, in rtl_hw_start_8168h_1()
3319 { 0x1d, 0x0000, 0x0800 }, in rtl_hw_start_8168h_1()
3320 { 0x05, 0xffff, 0x2089 }, in rtl_hw_start_8168h_1()
3321 { 0x06, 0xffff, 0x5881 }, in rtl_hw_start_8168h_1()
3322 { 0x04, 0xffff, 0x854a }, in rtl_hw_start_8168h_1()
3323 { 0x01, 0xffff, 0x068b } in rtl_hw_start_8168h_1()
3329 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168h_1()
3330 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168h_1()
3336 rtl_eri_set_bits(tp, 0xdc, 0x001c); in rtl_hw_start_8168h_1()
3338 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168h_1()
3342 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3343 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3352 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168h_1()
3356 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8168h_1()
3357 if (rg_saw_cnt > 0) { in rtl_hw_start_8168h_1()
3361 sw_cnt_1ms_ini &= 0x0fff; in rtl_hw_start_8168h_1()
3362 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8168h_1()
3365 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8168h_1()
3366 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); in rtl_hw_start_8168h_1()
3367 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); in rtl_hw_start_8168h_1()
3368 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8168h_1()
3370 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8168h_1()
3371 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8168h_1()
3372 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8168h_1()
3373 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8168h_1()
3380 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168ep()
3381 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8168ep()
3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168ep()
3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3396 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168ep()
3406 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8168ep_3()
3407 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8168ep_3()
3408 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8168ep_3()
3409 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168ep_3()
3419 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); in rtl_hw_start_8168ep_3()
3420 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8168ep_3()
3421 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8168ep_3()
3427 { 0x19, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3428 { 0x59, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3435 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8117()
3436 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8117()
3442 rtl_eri_set_bits(tp, 0xd4, 0x0010); in rtl_hw_start_8117()
3444 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8117()
3448 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3449 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3458 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8117()
3462 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8117()
3463 if (rg_saw_cnt > 0) { in rtl_hw_start_8117()
3466 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; in rtl_hw_start_8117()
3467 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8117()
3470 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8117()
3471 r8168_mac_ocp_write(tp, 0xea80, 0x0003); in rtl_hw_start_8117()
3472 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); in rtl_hw_start_8117()
3473 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8117()
3475 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8117()
3476 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8117()
3477 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8117()
3478 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8117()
3487 { 0x01, 0, 0x6e65 }, in rtl_hw_start_8102e_1()
3488 { 0x02, 0, 0x091f }, in rtl_hw_start_8102e_1()
3489 { 0x03, 0, 0xc2f9 }, in rtl_hw_start_8102e_1()
3490 { 0x06, 0, 0xafb5 }, in rtl_hw_start_8102e_1()
3491 { 0x07, 0, 0x0e00 }, in rtl_hw_start_8102e_1()
3492 { 0x19, 0, 0xec80 }, in rtl_hw_start_8102e_1()
3493 { 0x01, 0, 0x2e65 }, in rtl_hw_start_8102e_1()
3494 { 0x01, 0, 0x6e65 } in rtl_hw_start_8102e_1()
3525 rtl_ephy_write(tp, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
3531 { 0x01, 0xffff, 0x6fe5 }, in rtl_hw_start_8401()
3532 { 0x03, 0xffff, 0x0599 }, in rtl_hw_start_8401()
3533 { 0x06, 0xffff, 0xaf25 }, in rtl_hw_start_8401()
3534 { 0x07, 0xffff, 0x8e68 }, in rtl_hw_start_8401()
3544 { 0x07, 0, 0x4000 }, in rtl_hw_start_8105e_1()
3545 { 0x19, 0, 0x0200 }, in rtl_hw_start_8105e_1()
3546 { 0x19, 0, 0x0020 }, in rtl_hw_start_8105e_1()
3547 { 0x1e, 0, 0x2000 }, in rtl_hw_start_8105e_1()
3548 { 0x03, 0, 0x0001 }, in rtl_hw_start_8105e_1()
3549 { 0x19, 0, 0x0100 }, in rtl_hw_start_8105e_1()
3550 { 0x19, 0, 0x0004 }, in rtl_hw_start_8105e_1()
3551 { 0x0a, 0, 0x0020 } in rtl_hw_start_8105e_1()
3555 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3558 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3571 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
3577 { 0x19, 0xffff, 0xff64 }, in rtl_hw_start_8402()
3578 { 0x1e, 0, 0x4000 } in rtl_hw_start_8402()
3584 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3590 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); in rtl_hw_start_8402()
3592 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3593 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3594 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); in rtl_hw_start_8402()
3597 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3605 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3612 rtl_set_aspm_entry_latency(tp, 0x2f); in rtl_hw_start_8106()
3614 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3617 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3624 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); in DECLARE_RTL_COND()
3631 RTL_W16(tp, 0x382, 0x221b); in rtl_hw_start_8125_common()
3632 RTL_W8(tp, 0x4500, 0); in rtl_hw_start_8125_common()
3633 RTL_W16(tp, 0x4800, 0); in rtl_hw_start_8125_common()
3636 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); in rtl_hw_start_8125_common()
3638 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3640 r8168_mac_ocp_write(tp, 0xc140, 0xffff); in rtl_hw_start_8125_common()
3641 r8168_mac_ocp_write(tp, 0xc142, 0xffff); in rtl_hw_start_8125_common()
3643 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); in rtl_hw_start_8125_common()
3644 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8125_common()
3645 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8125_common()
3648 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3651 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); in rtl_hw_start_8125_common()
3653 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); in rtl_hw_start_8125_common()
3656 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); in rtl_hw_start_8125_common()
3658 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); in rtl_hw_start_8125_common()
3660 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); in rtl_hw_start_8125_common()
3661 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); in rtl_hw_start_8125_common()
3662 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); in rtl_hw_start_8125_common()
3663 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); in rtl_hw_start_8125_common()
3664 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); in rtl_hw_start_8125_common()
3665 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); in rtl_hw_start_8125_common()
3666 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); in rtl_hw_start_8125_common()
3667 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); in rtl_hw_start_8125_common()
3668 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); in rtl_hw_start_8125_common()
3670 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3671 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); in rtl_hw_start_8125_common()
3673 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3674 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); in rtl_hw_start_8125_common()
3676 r8168_mac_ocp_write(tp, 0xe098, 0xc302); in rtl_hw_start_8125_common()
3691 { 0x04, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3692 { 0x0a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3693 { 0x23, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3694 { 0x20, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3695 { 0x21, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3696 { 0x29, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3698 { 0x44, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3699 { 0x4a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3700 { 0x63, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3701 { 0x60, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3702 { 0x61, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3703 { 0x69, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3714 { 0x0b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3715 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3716 { 0x4b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3717 { 0x5e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3718 { 0x22, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3719 { 0x62, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3780 for (i = 0xa00; i < 0xb00; i += 4) in rtl_hw_start_8125()
3781 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3796 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8168()
3814 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8169()
3867 return 0; in rtl8169_change_mtu()
3874 desc->opts2 = 0; in rtl8169_mark_to_asic()
3892 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); in rtl8169_alloc_rx_data()
3909 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { in rtl8169_rx_clear()
3915 tp->RxDescArray[i].addr = 0; in rtl8169_rx_clear()
3916 tp->RxDescArray[i].opts1 = 0; in rtl8169_rx_clear()
3924 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_fill()
3938 return 0; in rtl8169_rx_fill()
3945 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); in rtl8169_init_ring()
3946 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); in rtl8169_init_ring()
3958 memset(desc, 0, sizeof(*desc)); in rtl8169_unmap_tx_skb()
3959 memset(tx_skb, 0, sizeof(*tx_skb)); in rtl8169_unmap_tx_skb()
3967 for (i = 0; i < n; i++) { in rtl8169_tx_clear_range()
4033 for (i = 0; i < NUM_RX_DESC; i++) in rtl_reset_work()
4067 opts1 = opts[0] | len; in rtl8169_tx_map()
4076 return 0; in rtl8169_tx_map()
4085 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { in rtl8169_xmit_frags()
4096 return 0; in rtl8169_xmit_frags()
4127 unsigned int padto = 0, len = skb->len; in rtl8125_quirk_udp_padto()
4154 unsigned int padto = 0; in rtl_quirk_packet_padto()
4182 opts[0] |= TD_LSO; in rtl8169_tso_csum_v1()
4183 opts[0] |= mss << TD0_MSS_SHIFT; in rtl8169_tso_csum_v1()
4188 opts[0] |= TD0_IP_CS | TD0_TCP_CS; in rtl8169_tso_csum_v1()
4190 opts[0] |= TD0_IP_CS | TD0_UDP_CS; in rtl8169_tso_csum_v1()
4204 opts[0] |= TD1_GTSENV4; in rtl8169_tso_csum_v2()
4206 if (skb_cow_head(skb, 0)) in rtl8169_tso_csum_v2()
4210 opts[0] |= TD1_GTSENV6; in rtl8169_tso_csum_v2()
4215 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; in rtl8169_tso_csum_v2()
4274 RTL_W16(tp, TxPoll_8125, BIT(0)); in rtl8169_doorbell()
4297 opts[0] = 0; in rtl8169_start_xmit()
4335 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), in rtl8169_start_xmit()
4423 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", in rtl8169_pcierr_interrupt()
4432 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; in rtl_tx()
4460 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, in rtl_tx()
4496 for (count = 0; count < budget; count++, tp->cur_rx++) { in rtl_rx()
4530 pkt_size = status & GENMASK(13, 0); in rtl_rx()
4582 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) in rtl8169_interrupt()
4623 if (RTL_R32(tp, TxConfig) == ~0) { in rtl_task()
4625 if (ret < 0) { in rtl_task()
4705 return 0; in r8169_phy_connect()
4770 return 0; in rtl8169_close()
4806 if (retval < 0) in rtl_open()
4813 if (retval < 0) in rtl_open()
4899 return 0; in rtl8169_runtime_resume()
4912 return 0; in rtl8169_suspend()
4935 return 0; in rtl8169_runtime_suspend()
4943 return 0; in rtl8169_runtime_suspend()
5063 value = rtl_eri_read(tp, 0xe0); in rtl_read_mac_address()
5065 value = rtl_eri_read(tp, 0xe4); in rtl_read_mac_address()
5086 if (phyaddr > 0) in r8169_mdio_read_reg()
5097 if (phyaddr > 0) in r8169_mdio_write_reg()
5102 return 0; in r8169_mdio_write_reg()
5118 r8169_mdio_write(tp, 0x1f, 0); in r8169_mdio_register()
5127 new_bus->irq[0] = PHY_MAC_INTERRUPT; in r8169_mdio_register()
5138 tp->phydev = mdiobus_get_phy(new_bus, 0); in r8169_mdio_register()
5145 …dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be… in r8169_mdio_register()
5157 return 0; in r8169_mdio_register()
5168 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8168g()
5171 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); in rtl_hw_init_8168g()
5183 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8125()
5186 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); in rtl_hw_init_8125()
5187 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); in rtl_hw_init_8125()
5188 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); in rtl_hw_init_8125()
5213 return 0; in rtl_jumbo_max()
5261 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) in rtl_aspm_is_safe()
5285 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; in rtl_init_one()
5305 if (rc < 0) in rtl_init_one()
5308 if (pcim_set_mwi(pdev) < 0) in rtl_init_one()
5313 if (region < 0) in rtl_init_one()
5317 if (rc < 0) in rtl_init_one()
5323 if (txconfig == ~0U) in rtl_init_one()
5326 xid = (txconfig >> 20) & 0xfcf; in rtl_init_one()
5340 rc = 0; in rtl_init_one()
5363 if (rc < 0) in rtl_init_one()
5366 tp->irq = pci_irq_vector(pdev, 0); in rtl_init_one()
5465 return 0; in rtl_init_one()