108 	u32 value;  in ql_sem_spinlock()  local
114 		value = readl(&port_regs->CommonRegs.semaphoreReg);  in ql_sem_spinlock()
115 		if ((value & (sem_mask >> 16)) == sem_bits)  in ql_sem_spinlock()
134 	u32 value;  in ql_sem_lock()  local
137 	value = readl(&port_regs->CommonRegs.semaphoreReg);  in ql_sem_lock()
138 	return ((value & (sem_mask >> 16)) == sem_bits);  in ql_sem_lock()
177 	u32 value;  in ql_read_common_reg_l()  local
181 	value = readl(reg);  in ql_read_common_reg_l()
184 	return value;  in ql_read_common_reg_l()
194 	u32 value;  in ql_read_page0_reg_l()  local
201 	value = readl(reg);  in ql_read_page0_reg_l()
204 	return value;  in ql_read_page0_reg_l()
215 				u32 __iomem *reg, u32 value)  in ql_write_common_reg_l()  argument
220 	writel(value, reg);  in ql_write_common_reg_l()
226 				u32 __iomem *reg, u32 value)  in ql_write_common_reg()  argument
228 	writel(value, reg);  in ql_write_common_reg()
233 				u32 __iomem *reg, u32 value)  in ql_write_nvram_reg()  argument
235 	writel(value, reg);  in ql_write_nvram_reg()
241 			       u32 __iomem *reg, u32 value)  in ql_write_page0_reg()  argument
245 	writel(value, reg);  in ql_write_page0_reg()
253 			       u32 __iomem *reg, u32 value)  in ql_write_page1_reg()  argument
257 	writel(value, reg);  in ql_write_page1_reg()
265 			       u32 __iomem *reg, u32 value)  in ql_write_page2_reg()  argument
269 	writel(value, reg);  in ql_write_page2_reg()
368 			    unsigned short *value);
472 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)  in fm93c56a_datain()  argument
494 	*value = (u16)data;  in fm93c56a_datain()
501 			    u32 eepromAddr, unsigned short *value)  in eeprom_readword()  argument
505 	fm93c56a_datain(qdev, value);  in eeprom_readword()
635 			       u16 regAddr, u16 value, u32 phyAddr)  in ql_mii_write_reg_ex()  argument
651 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);  in ql_mii_write_reg_ex()
666 			      u16 *value, u32 phyAddr)  in ql_mii_read_reg_ex()  argument
696 	*value = (u16) temp;  in ql_mii_read_reg_ex()
704 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)  in ql_mii_write_reg()  argument
719 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);  in ql_mii_write_reg()
732 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)  in ql_mii_read_reg()  argument
761 	*value = (u16) temp;  in ql_mii_read_reg()
1038 	u32 value;  in ql_mac_enable()  local
1041 		value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));  in ql_mac_enable()
1043 		value = (MAC_CONFIG_REG_PE << 16);  in ql_mac_enable()
1046 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);  in ql_mac_enable()
1048 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);  in ql_mac_enable()
1058 	u32 value;  in ql_mac_cfg_soft_reset()  local
1061 		value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));  in ql_mac_cfg_soft_reset()
1063 		value = (MAC_CONFIG_REG_SR << 16);  in ql_mac_cfg_soft_reset()
1066 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);  in ql_mac_cfg_soft_reset()
1068 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);  in ql_mac_cfg_soft_reset()
1078 	u32 value;  in ql_mac_cfg_gig()  local
1081 		value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));  in ql_mac_cfg_gig()
1083 		value = (MAC_CONFIG_REG_GM << 16);  in ql_mac_cfg_gig()
1086 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);  in ql_mac_cfg_gig()
1088 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);  in ql_mac_cfg_gig()
1098 	u32 value;  in ql_mac_cfg_full_dup()  local
1101 		value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));  in ql_mac_cfg_full_dup()
1103 		value = (MAC_CONFIG_REG_FD << 16);  in ql_mac_cfg_full_dup()
1106 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);  in ql_mac_cfg_full_dup()
1108 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);  in ql_mac_cfg_full_dup()
1118 	u32 value;  in ql_mac_cfg_pause()  local
1121 		value =  in ql_mac_cfg_pause()
1125 		value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);  in ql_mac_cfg_pause()
1128 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);  in ql_mac_cfg_pause()
1130 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);  in ql_mac_cfg_pause()
1752 static void ql_set_msglevel(struct net_device *ndev, u32 value)  in ql_set_msglevel()  argument
1755 	qdev->msg_enable = value;  in ql_set_msglevel()
2206 	u32 value;  in ql3xxx_isr()  local
2210 	value = ql_read_common_reg_l(qdev,  in ql3xxx_isr()
2213 	if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {  in ql3xxx_isr()
2221 		if (value & ISP_CONTROL_FE) {  in ql3xxx_isr()
2239 				   value);  in ql3xxx_isr()
2243 	} else if (value & ISP_IMR_DISABLE_CMPL_INT) {  in ql3xxx_isr()
2997 	u32 value;  in ql_adapter_initialize()  local
3122 	value = ql_read_page0_reg(qdev, &port_regs->portStatus);  in ql_adapter_initialize()
3123 	if ((value & PORT_STATUS_IC) == 0) {  in ql_adapter_initialize()
3131 		value = qdev->nvram_data.tcpMaxWindowSize;  in ql_adapter_initialize()
3132 		ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);  in ql_adapter_initialize()
3134 		value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;  in ql_adapter_initialize()
3142 		ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);  in ql_adapter_initialize()
3212 		value = ql_read_page0_reg(qdev, &port_regs->portStatus);  in ql_adapter_initialize()
3213 		if (value & PORT_STATUS_IC)  in ql_adapter_initialize()
3228 		value =  in ql_adapter_initialize()
3233 				   ((value << 16) | value));  in ql_adapter_initialize()
3235 		value =  in ql_adapter_initialize()
3239 				   ((value << 16) | value));  in ql_adapter_initialize()
3255 	u16 value;  in ql_adapter_reset()  local
3276 		value =  in ql_adapter_reset()
3279 		if ((value & ISP_CONTROL_SR) == 0)  in ql_adapter_reset()
3289 	value =  in ql_adapter_reset()
3291 	if (value & ISP_CONTROL_RI) {  in ql_adapter_reset()
3313 			value = ql_read_common_reg(qdev,  in ql_adapter_reset()
3316 			if ((value & ISP_CONTROL_FSR) == 0)  in ql_adapter_reset()
3333 	u32 value, port_status;  in ql_set_mac_info()  local
3337 	value =  in ql_set_mac_info()
3339 	func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);  in ql_set_mac_info()
3341 	switch (value & ISP_CONTROL_FN_MASK) {  in ql_set_mac_info()
3369 			      value);  in ql_set_mac_info()
3613 	u32 value;  in ql_reset_work()  local
3659 			value = ql_read_common_reg(qdev,  in ql_reset_work()
3663 			if ((value & ISP_CONTROL_SR) == 0) {  in ql_reset_work()
3669 			if (value & ISP_CONTROL_RI) {  in ql_reset_work()
3686 		if (value & ISP_CONTROL_SR) {  in ql_reset_work()
3720 	u32 value;  in ql_get_board_info()  local
3722 	value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);  in ql_get_board_info()
3724 	qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);  in ql_get_board_info()
3725 	if (value & PORT_STATUS_64)  in ql_get_board_info()
3729 	if (value & PORT_STATUS_X)  in ql_get_board_info()