Lines Matching refs:ATTENTION_SINGLE
59 #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) macro
60 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
574 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
575 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
576 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
577 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
591 {"PGLUE config_space", ATTENTION_SINGLE,
593 {"PGLUE misc_flr", ATTENTION_SINGLE,
597 {"PGLUE misc_mctp", ATTENTION_SINGLE,
599 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
600 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
601 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
619 {"General Attention 32", ATTENTION_SINGLE |
625 {"General Attention 35", ATTENTION_SINGLE |
633 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
641 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
644 {"MCP CPU", ATTENTION_SINGLE,
646 {"MCP Watchdog timer", ATTENTION_SINGLE,
648 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
649 {"AVS stop status ready", ATTENTION_SINGLE,
724 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
754 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
756 {"PERST_B assertion", ATTENTION_SINGLE,
758 {"PERST_B deassertion", ATTENTION_SINGLE,
769 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,