25 #define XAXIDMA_TX_CR_OFFSET	0x00 /* Channel control */  macro
357 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_hw_dma_bd_init()
367 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);  in nixge_hw_dma_bd_init()
384 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_hw_dma_bd_init()
385 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,  in nixge_hw_dma_bd_init()
416 	__nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_device_reset()
723 		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_tx_irq()
727 		nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);  in nixge_tx_irq()
772 		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_rx_irq()
776 		nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);  in nixge_rx_irq()
798 	__nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET);  in nixge_dma_err_handler()
835 	cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);  in nixge_dma_err_handler()
845 	nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr);  in nixge_dma_err_handler()
862 	cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);  in nixge_dma_err_handler()
863 	nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,  in nixge_dma_err_handler()
927 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_stop()
928 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,  in nixge_stop()
1010 	regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);  in nixge_ethtools_get_coalesce()