Lines Matching refs:val64
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ argument
1010 register u64 val64 = 0; in s2io_verify_pci_mode() local
1013 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1014 mode = (u8)GET_PCI_MODE(val64); in s2io_verify_pci_mode()
1016 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_verify_pci_mode()
1044 register u64 val64 = 0; in s2io_print_pci_mode() local
1049 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1050 mode = (u8)GET_PCI_MODE(val64); in s2io_print_pci_mode()
1052 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_print_pci_mode()
1094 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode); in s2io_print_pci_mode()
1114 register u64 val64 = 0; in init_tti() local
1126 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); in init_tti()
1128 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); in init_tti()
1130 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | in init_tti()
1136 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; in init_tti()
1137 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1140 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | in init_tti()
1151 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) | in init_tti()
1156 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | in init_tti()
1162 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1164 val64 = TTI_CMD_MEM_WE | in init_tti()
1167 writeq(val64, &bar0->tti_command_mem); in init_tti()
1191 register u64 val64 = 0; in init_nic() local
1211 val64 = 0xA500000000ULL; in init_nic()
1212 writeq(val64, &bar0->sw_reset); in init_nic()
1214 val64 = readq(&bar0->sw_reset); in init_nic()
1218 val64 = 0; in init_nic()
1219 writeq(val64, &bar0->sw_reset); in init_nic()
1221 val64 = readq(&bar0->sw_reset); in init_nic()
1228 val64 = readq(&bar0->adapter_status); in init_nic()
1229 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING)) in init_nic()
1239 val64 = readq(&bar0->mac_cfg); in init_nic()
1240 val64 |= MAC_RMAC_BCAST_ENABLE; in init_nic()
1242 writel((u32)val64, add); in init_nic()
1244 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1247 val64 = readq(&bar0->mac_int_mask); in init_nic()
1248 val64 = readq(&bar0->mc_int_mask); in init_nic()
1249 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1252 val64 = dev->mtu; in init_nic()
1253 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1267 val64 = readq(&bar0->dtx_control); in init_nic()
1273 val64 = 0; in init_nic()
1274 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1275 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1276 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1277 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1282 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) | in init_nic()
1292 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1293 val64 = 0; in init_nic()
1297 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1298 val64 = 0; in init_nic()
1302 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1303 val64 = 0; in init_nic()
1307 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1308 val64 = 0; in init_nic()
1324 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1326 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1332 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1333 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | in init_nic()
1337 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1340 val64 = 0; in init_nic()
1344 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3); in init_nic()
1346 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1352 val64 = 0; in init_nic()
1363 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); in init_nic()
1367 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); in init_nic()
1371 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); in init_nic()
1375 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); in init_nic()
1379 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); in init_nic()
1383 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); in init_nic()
1387 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); in init_nic()
1391 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); in init_nic()
1395 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1403 val64 = 0x0; in init_nic()
1404 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1405 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1406 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1407 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1408 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1411 val64 = 0x0001000100010001ULL; in init_nic()
1412 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1414 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1416 val64 = 0x0001000100000000ULL; in init_nic()
1417 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1420 val64 = 0x0001020001020001ULL; in init_nic()
1421 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1422 val64 = 0x0200010200010200ULL; in init_nic()
1423 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1424 val64 = 0x0102000102000102ULL; in init_nic()
1425 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1426 val64 = 0x0001020001020001ULL; in init_nic()
1427 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1428 val64 = 0x0200010200000000ULL; in init_nic()
1429 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1432 val64 = 0x0001020300010203ULL; in init_nic()
1433 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1435 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1437 val64 = 0x0001020300000000ULL; in init_nic()
1438 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1441 val64 = 0x0001020304000102ULL; in init_nic()
1442 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1443 val64 = 0x0304000102030400ULL; in init_nic()
1444 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1445 val64 = 0x0102030400010203ULL; in init_nic()
1446 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1447 val64 = 0x0400010203040001ULL; in init_nic()
1448 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1449 val64 = 0x0203040000000000ULL; in init_nic()
1450 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1453 val64 = 0x0001020304050001ULL; in init_nic()
1454 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1455 val64 = 0x0203040500010203ULL; in init_nic()
1456 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1457 val64 = 0x0405000102030405ULL; in init_nic()
1458 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1459 val64 = 0x0001020304050001ULL; in init_nic()
1460 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1461 val64 = 0x0203040500000000ULL; in init_nic()
1462 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1465 val64 = 0x0001020304050600ULL; in init_nic()
1466 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1467 val64 = 0x0102030405060001ULL; in init_nic()
1468 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1469 val64 = 0x0203040506000102ULL; in init_nic()
1470 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1471 val64 = 0x0304050600010203ULL; in init_nic()
1472 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1473 val64 = 0x0405060000000000ULL; in init_nic()
1474 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1477 val64 = 0x0001020304050607ULL; in init_nic()
1478 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1480 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1482 val64 = 0x0001020300000000ULL; in init_nic()
1483 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1488 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1489 val64 |= (TX_FIFO_PARTITION_EN); in init_nic()
1490 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1498 val64 = 0x0; in init_nic()
1499 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1500 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1501 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1502 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1503 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1505 val64 = 0x8080808080808080ULL; in init_nic()
1506 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1509 val64 = 0x0001000100010001ULL; in init_nic()
1510 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1511 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1512 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1513 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1514 val64 = 0x0001000100000000ULL; in init_nic()
1515 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1517 val64 = 0x8080808040404040ULL; in init_nic()
1518 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1521 val64 = 0x0001020001020001ULL; in init_nic()
1522 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1523 val64 = 0x0200010200010200ULL; in init_nic()
1524 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1525 val64 = 0x0102000102000102ULL; in init_nic()
1526 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1527 val64 = 0x0001020001020001ULL; in init_nic()
1528 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1529 val64 = 0x0200010200000000ULL; in init_nic()
1530 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1532 val64 = 0x8080804040402020ULL; in init_nic()
1533 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1536 val64 = 0x0001020300010203ULL; in init_nic()
1537 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1538 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1539 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1540 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1541 val64 = 0x0001020300000000ULL; in init_nic()
1542 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1544 val64 = 0x8080404020201010ULL; in init_nic()
1545 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1548 val64 = 0x0001020304000102ULL; in init_nic()
1549 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1550 val64 = 0x0304000102030400ULL; in init_nic()
1551 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1552 val64 = 0x0102030400010203ULL; in init_nic()
1553 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1554 val64 = 0x0400010203040001ULL; in init_nic()
1555 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1556 val64 = 0x0203040000000000ULL; in init_nic()
1557 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1559 val64 = 0x8080404020201008ULL; in init_nic()
1560 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1563 val64 = 0x0001020304050001ULL; in init_nic()
1564 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1565 val64 = 0x0203040500010203ULL; in init_nic()
1566 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1567 val64 = 0x0405000102030405ULL; in init_nic()
1568 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1569 val64 = 0x0001020304050001ULL; in init_nic()
1570 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1571 val64 = 0x0203040500000000ULL; in init_nic()
1572 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1574 val64 = 0x8080404020100804ULL; in init_nic()
1575 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1578 val64 = 0x0001020304050600ULL; in init_nic()
1579 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1580 val64 = 0x0102030405060001ULL; in init_nic()
1581 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1582 val64 = 0x0203040506000102ULL; in init_nic()
1583 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1584 val64 = 0x0304050600010203ULL; in init_nic()
1585 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1586 val64 = 0x0405060000000000ULL; in init_nic()
1587 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1589 val64 = 0x8080402010080402ULL; in init_nic()
1590 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1593 val64 = 0x0001020304050607ULL; in init_nic()
1594 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1595 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1596 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1597 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1598 val64 = 0x0001020300000000ULL; in init_nic()
1599 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1601 val64 = 0x8040201008040201ULL; in init_nic()
1602 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1607 val64 = 0; in init_nic()
1609 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1612 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); in init_nic()
1614 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1646 val64 = STAT_BC(0x320); in init_nic()
1647 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1654 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | in init_nic()
1656 writeq(val64, &bar0->mac_link_util); in init_nic()
1674 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); in init_nic()
1676 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); in init_nic()
1677 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | in init_nic()
1682 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1684 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | in init_nic()
1687 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | in init_nic()
1690 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | in init_nic()
1692 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1695 val64 = RTI_CMD_MEM_WE | in init_nic()
1698 writeq(val64, &bar0->rti_command_mem); in init_nic()
1709 val64 = readq(&bar0->rti_command_mem); in init_nic()
1710 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) in init_nic()
1732 val64 = readq(&bar0->mac_cfg); in init_nic()
1733 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); in init_nic()
1735 writel((u32) (val64), add); in init_nic()
1737 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1738 val64 = readq(&bar0->mac_cfg); in init_nic()
1742 val64 = readq(&bar0->mac_cfg); in init_nic()
1743 val64 |= MAC_CFG_RMAC_STRIP_FCS; in init_nic()
1745 writeq(val64, &bar0->mac_cfg); in init_nic()
1748 writel((u32) (val64), add); in init_nic()
1750 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1757 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1758 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); in init_nic()
1759 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); in init_nic()
1760 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1768 val64 = 0; in init_nic()
1770 val64 |= (((u64)0xFF00 | in init_nic()
1774 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1776 val64 = 0; in init_nic()
1778 val64 |= (((u64)0xFF00 | in init_nic()
1782 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1788 val64 = readq(&bar0->pic_control); in init_nic()
1789 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); in init_nic()
1790 writeq(val64, &bar0->pic_control); in init_nic()
1803 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | in init_nic()
1805 writeq(val64, &bar0->misc_control); in init_nic()
1806 val64 = readq(&bar0->pic_control2); in init_nic()
1807 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15)); in init_nic()
1808 writeq(val64, &bar0->pic_control2); in init_nic()
1811 val64 = TMAC_AVG_IPG(0x17); in init_nic()
1812 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
2079 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent() local
2085 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) in verify_pcc_quiescent()
2088 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) in verify_pcc_quiescent()
2093 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == in verify_pcc_quiescent()
2097 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == in verify_pcc_quiescent()
2121 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence() local
2124 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) { in verify_xena_quiescence()
2128 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { in verify_xena_quiescence()
2132 if (!(val64 & ADAPTER_STATUS_PFC_READY)) { in verify_xena_quiescence()
2136 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) { in verify_xena_quiescence()
2140 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) { in verify_xena_quiescence()
2144 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) { in verify_xena_quiescence()
2148 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) { in verify_xena_quiescence()
2152 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) { in verify_xena_quiescence()
2162 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && in verify_xena_quiescence()
2168 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == in verify_xena_quiescence()
2213 register u64 val64 = 0; in start_nic() local
2225 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2227 val64 |= PRC_CTRL_RC_ENABLED; in start_nic()
2229 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; in start_nic()
2231 val64 |= PRC_CTRL_GROUP_READS; in start_nic()
2232 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); in start_nic()
2233 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000); in start_nic()
2234 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2239 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2240 val64 |= RX_PA_CFG_IGNORE_L2_ERR; in start_nic()
2241 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2245 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2246 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; in start_nic()
2247 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2256 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2257 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; in start_nic()
2258 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2259 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2264 val64 = readq(&bar0->adapter_control); in start_nic()
2265 val64 &= ~ADAPTER_ECC_EN; in start_nic()
2266 writeq(val64, &bar0->adapter_control); in start_nic()
2272 val64 = readq(&bar0->adapter_status); in start_nic()
2276 dev->name, (unsigned long long)val64); in start_nic()
2289 val64 = readq(&bar0->adapter_control); in start_nic()
2290 val64 |= ADAPTER_EOI_TX_ON; in start_nic()
2291 writeq(val64, &bar0->adapter_control); in start_nic()
2304 val64 = readq(&bar0->gpio_control); in start_nic()
2305 val64 |= 0x0000800000000000ULL; in start_nic()
2306 writeq(val64, &bar0->gpio_control); in start_nic()
2307 val64 = 0x0411040400000000ULL; in start_nic()
2308 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2415 register u64 val64 = 0; in stop_nic() local
2425 val64 = readq(&bar0->adapter_control); in stop_nic()
2426 val64 &= ~(ADAPTER_CNTL_EN); in stop_nic()
2427 writeq(val64, &bar0->adapter_control); in stop_nic()
2835 u64 val64 = 0xFFFFFFFFFFFFFFFFULL; in s2io_netpoll() local
2845 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2846 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3088 u64 val64; in s2io_mdio_write() local
3093 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3096 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3097 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3098 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3102 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3107 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3108 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3109 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3112 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3116 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3117 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3118 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3133 u64 val64 = 0x0; in s2io_mdio_read() local
3139 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr) in s2io_mdio_read()
3142 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3143 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read()
3144 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3148 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_read()
3152 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3153 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read()
3154 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3180 u64 val64; in s2io_chk_xpak_counter() local
3187 val64 = *regs_stat & mask; in s2io_chk_xpak_counter()
3188 val64 = val64 >> (index * 0x2); in s2io_chk_xpak_counter()
3189 val64 = val64 + 1; in s2io_chk_xpak_counter()
3190 if (val64 == 3) { in s2io_chk_xpak_counter()
3214 val64 = 0x0; in s2io_chk_xpak_counter()
3216 val64 = val64 << (index * 0x2); in s2io_chk_xpak_counter()
3217 *regs_stat = (*regs_stat & (~mask)) | (val64); in s2io_chk_xpak_counter()
3236 u64 val64 = 0x0; in s2io_updt_xpak_counter() local
3245 val64 = 0x0; in s2io_updt_xpak_counter()
3246 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3247 if ((val64 == 0xFFFF) || (val64 == 0x0000)) { in s2io_updt_xpak_counter()
3250 (unsigned long long)val64); in s2io_updt_xpak_counter()
3255 if (val64 != MDIO_CTRL1_SPEED10G) { in s2io_updt_xpak_counter()
3258 (unsigned long long)val64, MDIO_CTRL1_SPEED10G); in s2io_updt_xpak_counter()
3265 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3269 val64 = 0x0; in s2io_updt_xpak_counter()
3270 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3272 flag = CHECKBIT(val64, 0x7); in s2io_updt_xpak_counter()
3278 if (CHECKBIT(val64, 0x6)) in s2io_updt_xpak_counter()
3281 flag = CHECKBIT(val64, 0x3); in s2io_updt_xpak_counter()
3287 if (CHECKBIT(val64, 0x2)) in s2io_updt_xpak_counter()
3290 flag = CHECKBIT(val64, 0x1); in s2io_updt_xpak_counter()
3296 if (CHECKBIT(val64, 0x0)) in s2io_updt_xpak_counter()
3301 val64 = 0x0; in s2io_updt_xpak_counter()
3302 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3304 if (CHECKBIT(val64, 0x7)) in s2io_updt_xpak_counter()
3307 if (CHECKBIT(val64, 0x6)) in s2io_updt_xpak_counter()
3310 if (CHECKBIT(val64, 0x3)) in s2io_updt_xpak_counter()
3313 if (CHECKBIT(val64, 0x2)) in s2io_updt_xpak_counter()
3316 if (CHECKBIT(val64, 0x1)) in s2io_updt_xpak_counter()
3319 if (CHECKBIT(val64, 0x0)) in s2io_updt_xpak_counter()
3341 u64 val64; in wait_for_cmd_complete() local
3347 val64 = readq(addr); in wait_for_cmd_complete()
3349 if (!(val64 & busy_bit)) { in wait_for_cmd_complete()
3354 if (val64 & busy_bit) { in wait_for_cmd_complete()
3403 u64 val64; in s2io_reset() local
3418 val64 = SW_RESET_ALL; in s2io_reset()
3419 writeq(val64, &bar0->sw_reset); in s2io_reset()
3494 val64 = readq(&bar0->gpio_control); in s2io_reset()
3495 val64 |= 0x0000800000000000ULL; in s2io_reset()
3496 writeq(val64, &bar0->gpio_control); in s2io_reset()
3497 val64 = 0x0411040400000000ULL; in s2io_reset()
3498 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3506 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3507 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3527 u64 val64, valt, valr; in s2io_set_swapper() local
3534 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3535 if (val64 != 0x0123456789ABCDEFULL) { in s2io_set_swapper()
3546 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3547 if (val64 == 0x0123456789ABCDEFULL) in s2io_set_swapper()
3554 dev->name, (unsigned long long)val64); in s2io_set_swapper()
3564 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3566 if (val64 != valt) { in s2io_set_swapper()
3578 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3579 if (val64 == valt) in s2io_set_swapper()
3584 unsigned long long x = val64; in s2io_set_swapper()
3590 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3591 val64 &= 0xFFFF000000000000ULL; in s2io_set_swapper()
3598 val64 |= (SWAPPER_CTRL_TXP_FE | in s2io_set_swapper()
3610 val64 |= SWAPPER_CTRL_XMSI_SE; in s2io_set_swapper()
3611 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3618 val64 |= (SWAPPER_CTRL_TXP_FE | in s2io_set_swapper()
3634 val64 |= SWAPPER_CTRL_XMSI_SE; in s2io_set_swapper()
3635 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3637 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3643 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3644 if (val64 != 0x0123456789ABCDEFULL) { in s2io_set_swapper()
3648 dev->name, (unsigned long long)val64); in s2io_set_swapper()
3658 u64 val64; in wait_for_msix_trans() local
3662 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3663 if (!(val64 & s2BIT(15))) in wait_for_msix_trans()
3679 u64 val64; in restore_xmsi_data() local
3689 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6)); in restore_xmsi_data()
3690 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3700 u64 val64, addr, data; in store_xmsi_data() local
3709 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6)); in store_xmsi_data()
3710 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3826 u64 val64, saved64; in s2io_test_msi() local
3839 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3840 val64 |= SCHED_INT_CTRL_ONE_SHOT; in s2io_test_msi()
3841 val64 |= SCHED_INT_CTRL_TIMER_EN; in s2io_test_msi()
3842 val64 |= SCHED_INT_CTRL_INT2MSI(1); in s2io_test_msi()
3843 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4011 register u64 val64; in s2io_xmit() local
4154 val64 = fifo->list_info[put_off].list_phy_addr; in s2io_xmit()
4155 writeq(val64, &tx_fifo->TxDL_Pointer); in s2io_xmit()
4157 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | in s2io_xmit()
4160 val64 |= TX_FIFO_SPECIAL_FUNC; in s2io_xmit()
4162 writeq(val64, &tx_fifo->List_Control); in s2io_xmit()
4271 u64 val64; in s2io_txpic_intr_handle() local
4273 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4274 if (val64 & PIC_INT_GPIO) { in s2io_txpic_intr_handle()
4275 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4276 if ((val64 & GPIO_INT_REG_LINK_DOWN) && in s2io_txpic_intr_handle()
4277 (val64 & GPIO_INT_REG_LINK_UP)) { in s2io_txpic_intr_handle()
4282 val64 |= GPIO_INT_REG_LINK_DOWN; in s2io_txpic_intr_handle()
4283 val64 |= GPIO_INT_REG_LINK_UP; in s2io_txpic_intr_handle()
4284 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4285 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4286 val64 &= ~(GPIO_INT_MASK_LINK_UP | in s2io_txpic_intr_handle()
4288 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4289 } else if (val64 & GPIO_INT_REG_LINK_UP) { in s2io_txpic_intr_handle()
4290 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4292 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4293 val64 |= ADAPTER_CNTL_EN; in s2io_txpic_intr_handle()
4294 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4295 val64 |= ADAPTER_LED_ON; in s2io_txpic_intr_handle()
4296 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4305 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4306 val64 &= ~GPIO_INT_MASK_LINK_DOWN; in s2io_txpic_intr_handle()
4307 val64 |= GPIO_INT_MASK_LINK_UP; in s2io_txpic_intr_handle()
4308 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4310 } else if (val64 & GPIO_INT_REG_LINK_DOWN) { in s2io_txpic_intr_handle()
4311 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4314 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4315 val64 &= ~GPIO_INT_MASK_LINK_UP; in s2io_txpic_intr_handle()
4316 val64 |= GPIO_INT_MASK_LINK_DOWN; in s2io_txpic_intr_handle()
4317 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4320 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4321 val64 = val64 & (~ADAPTER_LED_ON); in s2io_txpic_intr_handle()
4322 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4325 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4341 u64 val64; in do_s2io_chk_alarm_bit() local
4342 val64 = readq(addr); in do_s2io_chk_alarm_bit()
4343 if (val64 & value) { in do_s2io_chk_alarm_bit()
4344 writeq(val64, addr); in do_s2io_chk_alarm_bit()
4365 u64 temp64 = 0, val64 = 0; in s2io_handle_errors() local
4392 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4393 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4394 if (val64 & RMAC_LINK_STATE_CHANGE_INT) in s2io_handle_errors()
4410 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4412 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); in s2io_handle_errors()
4417 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4419 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); in s2io_handle_errors()
4425 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4427 if (val64 & TXDMA_PFC_INT) { in s2io_handle_errors()
4440 if (val64 & TXDMA_TDA_INT) { in s2io_handle_errors()
4452 if (val64 & TXDMA_PCC_INT) { in s2io_handle_errors()
4467 if (val64 & TXDMA_TTI_INT) { in s2io_handle_errors()
4478 if (val64 & TXDMA_LSO_INT) { in s2io_handle_errors()
4490 if (val64 & TXDMA_TPA_INT) { in s2io_handle_errors()
4501 if (val64 & TXDMA_SM_INT) { in s2io_handle_errors()
4508 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4509 if (val64 & MAC_INT_STATUS_TMAC_INT) { in s2io_handle_errors()
4521 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4522 if (val64 & XGXS_INT_STATUS_TXGXS) { in s2io_handle_errors()
4532 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4533 if (val64 & RXDMA_INT_RC_INT_M) { in s2io_handle_errors()
4558 if (val64 & RXDMA_INT_RPA_INT_M) { in s2io_handle_errors()
4568 if (val64 & RXDMA_INT_RDA_INT_M) { in s2io_handle_errors()
4585 if (val64 & RXDMA_INT_RTI_INT_M) { in s2io_handle_errors()
4595 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4596 if (val64 & MAC_INT_STATUS_RMAC_INT) { in s2io_handle_errors()
4608 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4609 if (val64 & XGXS_INT_STATUS_RXGXS) { in s2io_handle_errors()
4616 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4617 if (val64 & MC_INT_STATUS_MC_INT) { in s2io_handle_errors()
4624 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { in s2io_handle_errors()
4625 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4626 if (val64 & MC_ERR_REG_ECC_ALL_DBL) { in s2io_handle_errors()
4632 if (val64 & in s2io_handle_errors()
4764 u64 val64; in s2io_updt_stats() local
4769 val64 = SET_UPDT_CLICKS(10) | in s2io_updt_stats()
4771 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4774 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4775 if (!(val64 & s2BIT(0))) in s2io_updt_stats()
4892 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = in s2io_set_multicast() local
4904 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4907 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4921 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4924 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4937 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4938 val64 |= MAC_CFG_RMAC_PROM_ENABLE; in s2io_set_multicast()
4941 writel((u32)val64, add); in s2io_set_multicast()
4943 writel((u32) (val64 >> 32), (add + 4)); in s2io_set_multicast()
4946 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4947 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; in s2io_set_multicast()
4948 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4952 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4959 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4960 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; in s2io_set_multicast()
4963 writel((u32)val64, add); in s2io_set_multicast()
4965 writel((u32) (val64 >> 32), (add + 4)); in s2io_set_multicast()
4968 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4969 val64 |= RX_PA_CFG_STRIP_VLAN_TAG; in s2io_set_multicast()
4970 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4974 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4999 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
5003 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5029 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
5033 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5125 u64 val64; in do_s2io_add_mac() local
5131 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in do_s2io_add_mac()
5133 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5171 u64 tmp64, val64; in do_s2io_read_unicast_mc() local
5175 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in do_s2io_read_unicast_mc()
5177 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5386 u64 val64; in s2io_set_led() local
5390 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5392 val64 |= GPIO_CTRL_GPIO_0; in s2io_set_led()
5394 val64 &= ~GPIO_CTRL_GPIO_0; in s2io_set_led()
5396 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5398 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5400 val64 |= ADAPTER_LED_ON; in s2io_set_led()
5402 val64 &= ~ADAPTER_LED_ON; in s2io_set_led()
5404 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5429 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led() local
5430 if (!(val64 & ADAPTER_CNTL_EN)) { in s2io_ethtool_set_led()
5499 u64 val64; in s2io_ethtool_getpause_data() local
5503 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5504 if (val64 & RMAC_PAUSE_GEN_ENABLE) in s2io_ethtool_getpause_data()
5506 if (val64 & RMAC_PAUSE_RX_ENABLE) in s2io_ethtool_getpause_data()
5525 u64 val64; in s2io_ethtool_setpause_data() local
5529 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5531 val64 |= RMAC_PAUSE_GEN_ENABLE; in s2io_ethtool_setpause_data()
5533 val64 &= ~RMAC_PAUSE_GEN_ENABLE; in s2io_ethtool_setpause_data()
5535 val64 |= RMAC_PAUSE_RX_ENABLE; in s2io_ethtool_setpause_data()
5537 val64 &= ~RMAC_PAUSE_RX_ENABLE; in s2io_ethtool_setpause_data()
5538 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5562 u64 val64; in read_eeprom() local
5566 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | in read_eeprom()
5571 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5574 val64 = readq(&bar0->i2c_control); in read_eeprom()
5575 if (I2C_CONTROL_CNTL_END(val64)) { in read_eeprom()
5576 *data = I2C_CONTROL_GET_DATA(val64); in read_eeprom()
5586 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | in read_eeprom()
5589 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5590 val64 |= SPI_CONTROL_REQ; in read_eeprom()
5591 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5593 val64 = readq(&bar0->spi_control); in read_eeprom()
5594 if (val64 & SPI_CONTROL_NACK) { in read_eeprom()
5597 } else if (val64 & SPI_CONTROL_DONE) { in read_eeprom()
5628 u64 val64; in write_eeprom() local
5632 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | in write_eeprom()
5637 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5640 val64 = readq(&bar0->i2c_control); in write_eeprom()
5641 if (I2C_CONTROL_CNTL_END(val64)) { in write_eeprom()
5642 if (!(val64 & I2C_CONTROL_NACK)) in write_eeprom()
5655 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | in write_eeprom()
5658 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5659 val64 |= SPI_CONTROL_REQ; in write_eeprom()
5660 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5662 val64 = readq(&bar0->spi_control); in write_eeprom()
5663 if (val64 & SPI_CONTROL_NACK) { in write_eeprom()
5666 } else if (val64 & SPI_CONTROL_DONE) { in write_eeprom()
5849 u64 val64 = 0, exp_val; in s2io_register_test() local
5852 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5853 if (val64 != 0x123456789abcdefULL) { in s2io_register_test()
5858 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5859 if (val64 != 0xc000ffff00000000ULL) { in s2io_register_test()
5864 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5869 if (val64 != exp_val) { in s2io_register_test()
5874 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5875 if (val64 != 0x000000001923141EULL) { in s2io_register_test()
5880 val64 = 0x5A5A5A5A5A5A5A5AULL; in s2io_register_test()
5881 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5882 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5883 if (val64 != 0x5A5A5A5A5A5A5A5AULL) { in s2io_register_test()
5888 val64 = 0xA5A5A5A5A5A5A5A5ULL; in s2io_register_test()
5889 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5890 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5891 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { in s2io_register_test()
6054 u64 val64; in s2io_link_test() local
6056 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6057 if (!(LINK_IS_UP(val64))) in s2io_link_test()
6081 u64 val64; in s2io_rldram_test() local
6084 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6085 val64 &= ~ADAPTER_ECC_EN; in s2io_rldram_test()
6086 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6088 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6089 val64 |= MC_RLDRAM_TEST_MODE; in s2io_rldram_test()
6090 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6092 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6093 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; in s2io_rldram_test()
6094 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6096 val64 |= MC_RLDRAM_MRS_ENABLE; in s2io_rldram_test()
6097 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6100 val64 = 0x55555555aaaa0000ULL; in s2io_rldram_test()
6102 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6103 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6105 val64 = 0xaaaa5a5555550000ULL; in s2io_rldram_test()
6107 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6108 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6110 val64 = 0x55aaaaaaaa5a0000ULL; in s2io_rldram_test()
6112 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6113 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6115 val64 = (u64) (0x0000003ffffe0100ULL); in s2io_rldram_test()
6116 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6118 val64 = MC_RLDRAM_TEST_MODE | in s2io_rldram_test()
6121 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6124 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6125 if (val64 & MC_RLDRAM_TEST_DONE) in s2io_rldram_test()
6133 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; in s2io_rldram_test()
6134 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6137 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6138 if (val64 & MC_RLDRAM_TEST_DONE) in s2io_rldram_test()
6146 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6147 if (!(val64 & MC_RLDRAM_TEST_PASS)) in s2io_rldram_test()
6652 u64 val64 = new_mtu; in s2io_change_mtu() local
6654 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6672 register u64 val64; in s2io_set_link() local
6694 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6695 if (LINK_IS_UP(val64)) { in s2io_set_link()
6698 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6699 val64 |= ADAPTER_CNTL_EN; in s2io_set_link()
6700 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6703 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6704 val64 |= GPIO_CTRL_GPIO_0; in s2io_set_link()
6705 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6706 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6708 val64 |= ADAPTER_LED_ON; in s2io_set_link()
6709 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6719 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6720 val64 |= ADAPTER_LED_ON; in s2io_set_link()
6721 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6726 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6727 val64 &= ~GPIO_CTRL_GPIO_0; in s2io_set_link()
6728 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6729 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6732 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6733 val64 = val64 & (~ADAPTER_LED_ON); in s2io_set_link()
6734 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7014 register u64 val64 = 0; in do_s2io_card_down() local
7058 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7069 (unsigned long long)val64); in do_s2io_card_down()
7608 register u64 val64 = 0; in rts_ds_steer() local
7613 val64 = RTS_DS_MEM_DATA(ring); in rts_ds_steer()
7614 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7616 val64 = RTS_DS_MEM_CTRL_WE | in rts_ds_steer()
7620 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7665 u64 val64 = 0, tmp64 = 0; in s2io_init_nic() local
7932 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in s2io_init_nic()
7934 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
8000 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8001 val64 |= 0x0000800000000000ULL; in s2io_init_nic()
8002 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8003 val64 = 0x0411040400000000ULL; in s2io_init_nic()
8004 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8005 val64 = readq(&bar0->gpio_control); in s2io_init_nic()