Lines Matching refs:dev
450 static inline struct ns83820 *PRIV(struct net_device *dev) in PRIV() argument
452 return netdev_priv(dev); in PRIV()
455 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) argument
459 struct ns83820 *dev = PRIV(ndev); in kick_rx() local
461 if (test_and_clear_bit(0, &dev->rx_info.idle)) { in kick_rx()
463 writel(dev->rx_info.phy_descs + in kick_rx()
464 (4 * DESC_SIZE * dev->rx_info.next_rx), in kick_rx()
465 dev->base + RXDP); in kick_rx()
466 if (dev->rx_info.next_rx == dev->rx_info.next_empty) in kick_rx()
469 __kick_rx(dev); in kick_rx()
474 #define start_tx_okay(dev) \ argument
475 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
490 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf… in build_rx_desc() argument
499 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_D… argument
500 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb) in ns83820_add_rx_skb() argument
507 next_empty = dev->rx_info.next_empty; in ns83820_add_rx_skb()
510 if (unlikely(nr_rx_empty(dev) <= 2)) { in ns83820_add_rx_skb()
517 dev->rx_info.next_empty, in ns83820_add_rx_skb()
518 dev->rx_info.nr_used, in ns83820_add_rx_skb()
519 dev->rx_info.next_rx in ns83820_add_rx_skb()
523 sg = dev->rx_info.descs + (next_empty * DESC_SIZE); in ns83820_add_rx_skb()
524 BUG_ON(NULL != dev->rx_info.skbs[next_empty]); in ns83820_add_rx_skb()
525 dev->rx_info.skbs[next_empty] = skb; in ns83820_add_rx_skb()
527 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC; in ns83820_add_rx_skb()
529 buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE, in ns83820_add_rx_skb()
531 build_rx_desc(dev, sg, 0, buf, cmdsts, 0); in ns83820_add_rx_skb()
533 if (likely(next_empty != dev->rx_info.next_rx)) in ns83820_add_rx_skb()
534 …dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx… in ns83820_add_rx_skb()
541 struct ns83820 *dev = PRIV(ndev); in rx_refill() local
545 if (unlikely(nr_rx_empty(dev) <= 2)) in rx_refill()
550 spin_lock_irqsave(&dev->rx_info.lock, flags); in rx_refill()
562 spin_lock_irqsave(&dev->rx_info.lock, flags); in rx_refill()
563 res = ns83820_add_rx_skb(dev, skb); in rx_refill()
565 spin_unlock_irqrestore(&dev->rx_info.lock, flags); in rx_refill()
572 spin_unlock_irqrestore(&dev->rx_info.lock, flags); in rx_refill()
585 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill); in queue_refill() local
586 struct net_device *ndev = dev->ndev; in queue_refill()
589 if (dev->rx_info.up) in queue_refill()
593 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i) in clear_rx_desc() argument
595 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0); in clear_rx_desc()
600 struct ns83820 *dev = PRIV(ndev); in phy_intr() local
606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; in phy_intr()
608 if (dev->CFG_cache & CFG_TBI_EN) { in phy_intr()
612 tbisr = readl(dev->base + TBISR); in phy_intr()
613 tanar = readl(dev->base + TANAR); in phy_intr()
614 tanlpar = readl(dev->base + TANLPAR); in phy_intr()
622 writel(readl(dev->base + TXCFG) in phy_intr()
624 dev->base + TXCFG); in phy_intr()
625 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
626 dev->base + RXCFG); in phy_intr()
628 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, in phy_intr()
629 dev->base + GPIOR); in phy_intr()
639 writel((readl(dev->base + TXCFG) in phy_intr()
641 dev->base + TXCFG); in phy_intr()
642 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, in phy_intr()
643 dev->base + RXCFG); in phy_intr()
645 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, in phy_intr()
646 dev->base + GPIOR); in phy_intr()
653 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); in phy_intr()
665 writel(readl(dev->base + TXCFG) in phy_intr()
667 dev->base + TXCFG); in phy_intr()
668 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
669 dev->base + RXCFG); in phy_intr()
671 writel(readl(dev->base + TXCFG) in phy_intr()
673 dev->base + TXCFG); in phy_intr()
674 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), in phy_intr()
675 dev->base + RXCFG); in phy_intr()
679 ((new_cfg ^ dev->CFG_cache) != 0)) { in phy_intr()
680 writel(new_cfg, dev->base + CFG); in phy_intr()
681 dev->CFG_cache = new_cfg; in phy_intr()
684 dev->CFG_cache &= ~CFG_SPDSTS; in phy_intr()
685 dev->CFG_cache |= cfg & CFG_SPDSTS; in phy_intr()
691 dev->linkstate != newlinkstate) { in phy_intr()
699 dev->linkstate != newlinkstate) { in phy_intr()
704 dev->linkstate = newlinkstate; in phy_intr()
709 struct ns83820 *dev = PRIV(ndev); in ns83820_setup_rx() local
715 dev->rx_info.idle = 1; in ns83820_setup_rx()
716 dev->rx_info.next_rx = 0; in ns83820_setup_rx()
717 dev->rx_info.next_rx_desc = dev->rx_info.descs; in ns83820_setup_rx()
718 dev->rx_info.next_empty = 0; in ns83820_setup_rx()
721 clear_rx_desc(dev, i); in ns83820_setup_rx()
723 writel(0, dev->base + RXDP_HI); in ns83820_setup_rx()
724 writel(dev->rx_info.phy_descs, dev->base + RXDP); in ns83820_setup_rx()
730 spin_lock_irq(&dev->rx_info.lock); in ns83820_setup_rx()
732 writel(0x0001, dev->base + CCSR); in ns83820_setup_rx()
733 writel(0, dev->base + RFCR); in ns83820_setup_rx()
734 writel(0x7fc00000, dev->base + RFCR); in ns83820_setup_rx()
735 writel(0xffc00000, dev->base + RFCR); in ns83820_setup_rx()
737 dev->rx_info.up = 1; in ns83820_setup_rx()
742 spin_lock(&dev->misc_lock); in ns83820_setup_rx()
743 dev->IMR_cache |= ISR_PHY; in ns83820_setup_rx()
744 dev->IMR_cache |= ISR_RXRCMP; in ns83820_setup_rx()
747 dev->IMR_cache |= ISR_RXORN; in ns83820_setup_rx()
748 dev->IMR_cache |= ISR_RXSOVR; in ns83820_setup_rx()
749 dev->IMR_cache |= ISR_RXDESC; in ns83820_setup_rx()
750 dev->IMR_cache |= ISR_RXIDLE; in ns83820_setup_rx()
751 dev->IMR_cache |= ISR_TXDESC; in ns83820_setup_rx()
752 dev->IMR_cache |= ISR_TXIDLE; in ns83820_setup_rx()
754 writel(dev->IMR_cache, dev->base + IMR); in ns83820_setup_rx()
755 writel(1, dev->base + IER); in ns83820_setup_rx()
756 spin_unlock(&dev->misc_lock); in ns83820_setup_rx()
760 spin_unlock_irq(&dev->rx_info.lock); in ns83820_setup_rx()
765 static void ns83820_cleanup_rx(struct ns83820 *dev) in ns83820_cleanup_rx() argument
770 dprintk("ns83820_cleanup_rx(%p)\n", dev); in ns83820_cleanup_rx()
773 spin_lock_irqsave(&dev->misc_lock, flags); in ns83820_cleanup_rx()
774 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE); in ns83820_cleanup_rx()
775 writel(dev->IMR_cache, dev->base + IMR); in ns83820_cleanup_rx()
776 spin_unlock_irqrestore(&dev->misc_lock, flags); in ns83820_cleanup_rx()
779 dev->rx_info.up = 0; in ns83820_cleanup_rx()
780 synchronize_irq(dev->pci_dev->irq); in ns83820_cleanup_rx()
783 readl(dev->base + IMR); in ns83820_cleanup_rx()
786 writel(0, dev->base + RXDP_HI); in ns83820_cleanup_rx()
787 writel(0, dev->base + RXDP); in ns83820_cleanup_rx()
790 struct sk_buff *skb = dev->rx_info.skbs[i]; in ns83820_cleanup_rx()
791 dev->rx_info.skbs[i] = NULL; in ns83820_cleanup_rx()
792 clear_rx_desc(dev, i); in ns83820_cleanup_rx()
799 struct ns83820 *dev = PRIV(ndev); in ns83820_rx_kick() local
801 if (dev->rx_info.up) { in ns83820_rx_kick()
807 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4) in ns83820_rx_kick()
808 schedule_work(&dev->tq_refill); in ns83820_rx_kick()
811 if (dev->rx_info.idle) in ns83820_rx_kick()
820 struct ns83820 *dev = PRIV(ndev); local
821 struct rx_info *info = &dev->rx_info;
831 readl(dev->base + RXDP),
832 (long)(dev->rx_info.phy_descs),
833 (int)dev->rx_info.next_rx,
834 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
835 (int)dev->rx_info.next_empty,
836 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
861 clear_rx_desc(dev, next_rx);
863 dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE,
930 struct ns83820 *dev = from_tasklet(dev, t, rx_tasklet); local
931 struct net_device *ndev = dev->ndev;
933 writel(ihr, dev->base + IHR);
935 spin_lock_irq(&dev->misc_lock);
936 dev->IMR_cache |= ISR_RXDESC;
937 writel(dev->IMR_cache, dev->base + IMR);
938 spin_unlock_irq(&dev->misc_lock);
946 static inline void kick_tx(struct ns83820 *dev) argument
949 dev, dev->tx_idx, dev->tx_free_idx);
950 writel(CR_TXE, dev->base + CR);
958 struct ns83820 *dev = PRIV(ndev); local
963 tx_done_idx = dev->tx_done_idx;
964 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
967 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
968 while ((tx_done_idx != dev->tx_free_idx) &&
982 tx_done_idx, dev->tx_free_idx, cmdsts);
983 skb = dev->tx_skbs[tx_done_idx];
984 dev->tx_skbs[tx_done_idx] = NULL;
990 dma_unmap_single(&dev->pci_dev->dev, addr, len,
993 atomic_dec(&dev->nr_tx_skbs);
995 dma_unmap_page(&dev->pci_dev->dev, addr, len,
999 dev->tx_done_idx = tx_done_idx;
1002 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1008 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1015 static void ns83820_cleanup_tx(struct ns83820 *dev) argument
1020 struct sk_buff *skb = dev->tx_skbs[i];
1021 dev->tx_skbs[i] = NULL;
1023 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1024 dma_unmap_single(&dev->pci_dev->dev,
1029 atomic_dec(&dev->nr_tx_skbs);
1033 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1045 struct ns83820 *dev = PRIV(ndev); local
1060 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1062 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1067 last_idx = free_idx = dev->tx_free_idx;
1068 tx_done_idx = dev->tx_done_idx;
1076 if (dev->tx_done_idx != tx_done_idx) {
1084 if (free_idx == dev->tx_intr_idx) {
1086 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1122 buf = dma_map_single(&dev->pci_dev->dev, skb->data, len,
1125 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1128 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1134 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1146 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1157 spin_lock_irq(&dev->tx_lock);
1158 dev->tx_skbs[last_idx] = skb;
1160 dev->tx_free_idx = free_idx;
1161 atomic_inc(&dev->nr_tx_skbs);
1162 spin_unlock_irq(&dev->tx_lock);
1164 kick_tx(dev);
1167 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1173 static void ns83820_update_stats(struct ns83820 *dev) argument
1175 struct net_device *ndev = dev->ndev;
1176 u8 __iomem *base = dev->base;
1194 struct ns83820 *dev = PRIV(ndev); local
1197 spin_lock_irq(&dev->misc_lock);
1198 ns83820_update_stats(dev);
1199 spin_unlock_irq(&dev->misc_lock);
1208 struct ns83820 *dev = PRIV(ndev); local
1227 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1228 readl(dev->base + TANAR);
1229 tbicr = readl(dev->base + TBICR);
1235 if (dev->CFG_cache & CFG_TBI_EN) {
1275 struct ns83820 *dev = PRIV(ndev); local
1281 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1282 tanar = readl(dev->base + TANAR);
1284 if (dev->CFG_cache & CFG_TBI_EN) {
1294 spin_lock_irq(&dev->misc_lock);
1295 spin_lock(&dev->tx_lock);
1303 writel(readl(dev->base + TXCFG)
1305 dev->base + TXCFG);
1306 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1307 dev->base + RXCFG);
1309 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1310 dev->base + GPIOR);
1328 dev->base + TBICR);
1329 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1330 dev->linkstate = LINK_AUTONEGOTIATE;
1336 writel(0x00000000, dev->base + TBICR);
1344 spin_unlock(&dev->tx_lock);
1345 spin_unlock_irq(&dev->misc_lock);
1353 struct ns83820 *dev = PRIV(ndev); local
1356 strscpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1361 struct ns83820 *dev = PRIV(ndev); local
1362 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1373 static inline void ns83820_disable_interrupts(struct ns83820 *dev) argument
1375 writel(0, dev->base + IMR);
1376 writel(0, dev->base + IER);
1377 readl(dev->base + IER);
1381 static void ns83820_mib_isr(struct ns83820 *dev) argument
1384 spin_lock_irqsave(&dev->misc_lock, flags);
1385 ns83820_update_stats(dev);
1386 spin_unlock_irqrestore(&dev->misc_lock, flags);
1393 struct ns83820 *dev = PRIV(ndev); local
1397 dev->ihr = 0;
1399 isr = readl(dev->base + ISR);
1407 struct ns83820 *dev = PRIV(ndev); local
1416 dev->rx_info.idle = 1;
1422 prefetch(dev->rx_info.next_rx_desc);
1424 spin_lock_irqsave(&dev->misc_lock, flags);
1425 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1426 writel(dev->IMR_cache, dev->base + IMR);
1427 spin_unlock_irqrestore(&dev->misc_lock, flags);
1429 tasklet_schedule(&dev->rx_tasklet);
1447 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1448 writel(CR_RXE, dev->base + CR);
1452 txdp = readl(dev->base + TXDP);
1454 txdp -= dev->tx_phy_descs;
1455 dev->tx_idx = txdp / (DESC_SIZE * 4);
1456 if (dev->tx_idx >= NR_TX_DESC) {
1458 dev->tx_idx = 0;
1465 if (dev->tx_idx != dev->tx_free_idx)
1466 kick_tx(dev);
1473 spin_lock_irqsave(&dev->tx_lock, flags);
1475 spin_unlock_irqrestore(&dev->tx_lock, flags);
1479 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1480 (dev->IMR_cache & ISR_TXOK)) {
1481 spin_lock_irqsave(&dev->misc_lock, flags);
1482 dev->IMR_cache &= ~ISR_TXOK;
1483 writel(dev->IMR_cache, dev->base + IMR);
1484 spin_unlock_irqrestore(&dev->misc_lock, flags);
1494 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1495 spin_lock_irqsave(&dev->misc_lock, flags);
1496 dev->IMR_cache |= ISR_TXOK;
1497 writel(dev->IMR_cache, dev->base + IMR);
1498 spin_unlock_irqrestore(&dev->misc_lock, flags);
1503 ns83820_mib_isr(dev);
1510 if (dev->ihr)
1511 writel(dev->ihr, dev->base + IHR);
1515 static void ns83820_do_reset(struct ns83820 *dev, u32 which) argument
1518 writel(which, dev->base + CR);
1521 } while (readl(dev->base + CR) & which);
1527 struct ns83820 *dev = PRIV(ndev); local
1530 del_timer_sync(&dev->tx_watchdog);
1532 ns83820_disable_interrupts(dev);
1534 dev->rx_info.up = 0;
1535 synchronize_irq(dev->pci_dev->irq);
1537 ns83820_do_reset(dev, CR_RST);
1539 synchronize_irq(dev->pci_dev->irq);
1541 spin_lock_irq(&dev->misc_lock);
1542 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1543 spin_unlock_irq(&dev->misc_lock);
1545 ns83820_cleanup_rx(dev);
1546 ns83820_cleanup_tx(dev);
1553 struct ns83820 *dev = PRIV(ndev); local
1558 spin_lock_irqsave(&dev->tx_lock, flags);
1560 tx_done_idx = dev->tx_done_idx;
1561 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1565 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1570 isr = readl(dev->base + ISR);
1571 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1578 tx_done_idx = dev->tx_done_idx;
1579 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1583 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1585 spin_unlock_irqrestore(&dev->tx_lock, flags);
1590 struct ns83820 *dev = from_timer(dev, t, tx_watchdog); local
1591 struct net_device *ndev = dev->ndev;
1595 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1600 dev->tx_done_idx != dev->tx_free_idx) {
1603 dev->tx_done_idx, dev->tx_free_idx,
1604 atomic_read(&dev->nr_tx_skbs));
1608 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1613 struct ns83820 *dev = PRIV(ndev); local
1620 writel(0, dev->base + PQCR);
1626 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1628 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1630 dev->tx_phy_descs
1634 dev->tx_idx = 0;
1635 dev->tx_done_idx = 0;
1636 desc = dev->tx_phy_descs;
1637 writel(0, dev->base + TXDP_HI);
1638 writel(desc, dev->base + TXDP);
1640 timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
1641 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1652 static void ns83820_getmac(struct ns83820 *dev, struct net_device *ndev) argument
1663 writel(i*2, dev->base + RFCR);
1664 data = readl(dev->base + RFDR);
1674 struct ns83820 *dev = PRIV(ndev); local
1675 u8 __iomem *rfcr = dev->base + RFCR;
1690 spin_lock_irq(&dev->misc_lock);
1695 spin_unlock_irq(&dev->misc_lock);
1700 struct ns83820 *dev = PRIV(ndev); local
1710 writel(enable, dev->base + PTSCR);
1713 status = readl(dev->base + PTSCR);
1738 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit) argument
1741 dev->MEAR_cache &= ~MEAR_MDC;
1742 writel(dev->MEAR_cache, dev->base + MEAR);
1743 readl(dev->base + MEAR);
1746 dev->MEAR_cache |= MEAR_MDDIR;
1748 dev->MEAR_cache |= MEAR_MDIO;
1750 dev->MEAR_cache &= ~MEAR_MDIO;
1753 writel(dev->MEAR_cache, dev->base + MEAR);
1754 readl(dev->base + MEAR);
1760 dev->MEAR_cache |= MEAR_MDC;
1761 writel(dev->MEAR_cache, dev->base + MEAR);
1762 readl(dev->base + MEAR);
1768 static int ns83820_mii_read_bit(struct ns83820 *dev) argument
1773 dev->MEAR_cache &= ~MEAR_MDC;
1774 dev->MEAR_cache &= ~MEAR_MDDIR;
1775 writel(dev->MEAR_cache, dev->base + MEAR);
1776 readl(dev->base + MEAR);
1782 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1783 dev->MEAR_cache |= MEAR_MDC;
1784 writel(dev->MEAR_cache, dev->base + MEAR);
1792 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg) argument
1799 ns83820_mii_read_bit(dev);
1801 ns83820_mii_write_bit(dev, 0); /* start */
1802 ns83820_mii_write_bit(dev, 1);
1803 ns83820_mii_write_bit(dev, 1); /* opcode read */
1804 ns83820_mii_write_bit(dev, 0);
1808 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1812 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1814 ns83820_mii_read_bit(dev); /* turn around cycles */
1815 ns83820_mii_read_bit(dev);
1820 data |= ns83820_mii_read_bit(dev);
1826 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned dat… argument
1832 ns83820_mii_read_bit(dev);
1834 ns83820_mii_write_bit(dev, 0); /* start */
1835 ns83820_mii_write_bit(dev, 1);
1836 ns83820_mii_write_bit(dev, 0); /* opcode read */
1837 ns83820_mii_write_bit(dev, 1);
1841 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1845 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1847 ns83820_mii_read_bit(dev); /* turn around cycles */
1848 ns83820_mii_read_bit(dev);
1852 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1859 struct ns83820 *dev = PRIV(ndev); local
1866 ns83820_mii_read_reg(dev, 1, 0 + j),
1867 ns83820_mii_read_reg(dev, 1, 1 + j),
1868 ns83820_mii_read_reg(dev, 1, 2 + j),
1869 ns83820_mii_read_reg(dev, 1, 3 + j)
1874 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1875 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1876 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1878 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1879 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1880 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1900 struct ns83820 *dev; local
1907 !dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) {
1909 } else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
1912 dev_warn(&pci_dev->dev, "dma_set_mask failed!\n");
1921 dev = PRIV(ndev);
1922 dev->ndev = ndev;
1924 spin_lock_init(&dev->rx_info.lock);
1925 spin_lock_init(&dev->tx_lock);
1926 spin_lock_init(&dev->misc_lock);
1927 dev->pci_dev = pci_dev;
1929 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1931 INIT_WORK(&dev->tq_refill, queue_refill);
1932 tasklet_setup(&dev->rx_tasklet, rx_action);
1936 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1942 dev->base = ioremap(addr, PAGE_SIZE);
1943 dev->tx_descs = dma_alloc_coherent(&pci_dev->dev,
1945 &dev->tx_phy_descs, GFP_KERNEL);
1946 dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev,
1948 &dev->rx_info.phy_descs, GFP_KERNEL);
1950 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1954 dev->tx_descs, (long)dev->tx_phy_descs,
1955 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1957 ns83820_disable_interrupts(dev);
1959 dev->IMR_cache = 0;
1964 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1979 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1984 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1992 ns83820_do_reset(dev, CR_RST);
1995 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2003 dev->CFG_cache = readl(dev->base + CFG);
2005 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2009 if (!(dev->CFG_cache & CFG_DATA64_EN))
2013 dev->CFG_cache &= ~(CFG_DATA64_EN);
2015 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2018 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2020 dev->CFG_cache |= CFG_REQALG;
2021 dev->CFG_cache |= CFG_POW;
2022 dev->CFG_cache |= CFG_TMRTEST;
2028 dev->CFG_cache |= CFG_M64ADDR;
2030 dev->CFG_cache |= CFG_T64ADDR;
2033 dev->CFG_cache &= ~CFG_BEM;
2036 if (dev->CFG_cache & CFG_TBI_EN) {
2039 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2042 writel(readl(dev->base + TANAR)
2044 dev->base + TANAR);
2048 dev->base + TBICR);
2049 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2050 dev->linkstate = LINK_AUTONEGOTIATE;
2052 dev->CFG_cache |= CFG_MODE_1000;
2055 writel(dev->CFG_cache, dev->base + CFG);
2056 dprintk("CFG: %08x\n", dev->CFG_cache);
2060 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2062 writel(dev->CFG_cache, dev->base + CFG);
2068 if (readl(dev->base + SRR))
2069 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2081 dev->base + TXCFG);
2084 writel(0x000, dev->base + IHR);
2085 writel(0x100, dev->base + IHR);
2086 writel(0x000, dev->base + IHR);
2097 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2100 writel(0, dev->base + PQCR);
2120 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2131 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2137 dev->base + PCR);
2140 writel(0, dev->base + WCSR);
2142 ns83820_getmac(dev, ndev);
2163 (unsigned)readl(dev->base + SRR) >> 8,
2164 (unsigned)readl(dev->base + SRR) & 0xff,
2183 ns83820_disable_interrupts(dev); /* paranoia */
2188 if (dev->base)
2189 iounmap(dev->base);
2190 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2191 dev->tx_descs, dev->tx_phy_descs);
2192 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2193 dev->rx_info.descs, dev->rx_info.phy_descs);
2204 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */ local
2209 ns83820_disable_interrupts(dev); /* paranoia */
2212 free_irq(dev->pci_dev->irq, ndev);
2213 iounmap(dev->base);
2214 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2215 dev->tx_descs, dev->tx_phy_descs);
2216 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2217 dev->rx_info.descs, dev->rx_info.phy_descs);
2218 pci_disable_device(dev->pci_dev);