276 	WOLCmd			= 0x40,  enumerator
1406 	wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;  in natsemi_reset()
1444 	wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;  in natsemi_reset()
1445 	writel(wcsr, ioaddr + WOLCmd);  in natsemi_reset()
1760 			dev->name, readl(ioaddr + WOLCmd));  in init_registers()
2433 		int wol_status = readl(ioaddr + WOLCmd);  in netdev_error()
2706 	u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;  in netdev_set_wol()
2727 	writel(data, ioaddr + WOLCmd);  in netdev_set_wol()
2736 	u32 regval = readl(ioaddr + WOLCmd);  in netdev_get_wol()
3140 	readl(ioaddr + WOLCmd);  in enable_wol_mode()
3219 		u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;  in netdev_close()
3302 			u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;  in natsemi_suspend()