Lines Matching +full:1 +full:g
19 TARGET_ANA_AC = 1,
62 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
64 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1)
78 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
87 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ argument
88 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
91 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ argument
92 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
95 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ argument
96 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
105 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ argument
106 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
109 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ argument
110 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
113 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ argument
114 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
123 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ argument
124 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
132 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1)
146 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4)
161 #define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\ argument
162 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4)
176 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1)
190 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4)
204 #define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1)
218 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4)
234 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4)
250 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4)
254 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4)
258 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4)
316 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4)
320 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4)
324 0, 1, 851584, 0, 1, 128, 0, r, 4, 4)
340 0, 1, 851584, 0, 1, 128, 16, r, 4, 4)
344 0, 1, 851584, 0, 1, 128, 32, r, 4, 4)
348 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4)
352 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4)
356 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4)
390 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4)
394 0, 1, 851552, 0, 1, 20, 0, r, 4, 4)
404 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4)
413 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\ argument
414 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
422 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1)
435 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\ argument
436 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
440 0, 1, 893792, 0, 1, 24, 0, r, 2, 4)
450 0, 1, 893792, 0, 1, 24, 8, r, 2, 4)
460 0, 1, 893792, 0, 1, 24, 16, r, 2, 4)
470 0, 1, 32768, 0, 1, 592, 0, r, 70, 4)
558 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4)
578 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1)
592 0, 1, 32768, 0, 1, 592, 424, r, 4, 4)
608 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4)
630 0, 1, 32768, 0, 1, 592, 580, r, 3, 4)
639 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\ argument
640 0, 1, 34200, g, 134, 16, 0, r, 4, 4)
678 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1)
691 #define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\ argument
692 0, 1, 0, g, 4096, 4, 0, 0, 1, 4)
695 #define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\ argument
696 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4)
700 0, 1, 36408, 0, 1, 16, 0, r, 4, 4)
798 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1)
812 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4)
822 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4)
836 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1)
850 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4)
864 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1)
877 #define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\ argument
878 0, 1, 295468, g, 10, 24, 0, 0, 1, 4)
887 #define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\ argument
888 0, 1, 295468, g, 10, 24, 4, 0, 1, 4)
897 #define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\ argument
898 0, 1, 295468, g, 10, 24, 8, 0, 1, 4)
913 #define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ argument
914 0, 1, 295468, g, 10, 24, 12, 0, 1, 4)
923 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\ argument
924 0, 1, 295468, g, 10, 24, 16, 0, 1, 4)
933 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\ argument
934 0, 1, 295468, g, 10, 24, 20, 0, 1, 4)
942 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1)
955 #define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\ argument
956 0, 1, 0, g, 4616, 64, 0, r, 2, 4)
965 #define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\ argument
966 0, 1, 0, g, 4616, 64, 8, r, 2, 4)
981 #define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\ argument
982 0, 1, 0, g, 4616, 64, 16, 0, 1, 4)
997 #define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\ argument
998 0, 1, 0, g, 4616, 64, 20, r, 2, 4)
1019 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1020 0, 1, 0, g, 4616, 64, 28, 0, 1, 4)
1029 #define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1030 0, 1, 0, g, 4616, 64, 32, 0, 1, 4)
1051 #define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1052 0, 1, 0, g, 4616, 64, 36, 0, 1, 4)
1096 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0)
1103 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ argument
1104 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
1112 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1)
1125 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\ argument
1126 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
1182 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1)
1195 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ argument
1196 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
1198 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
1211 #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\ argument
1212 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
1281 #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\ argument
1282 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
1284 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0)
1291 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\ argument
1292 0, 1, 131072, g, 70, 512, 108, r, 16, 4)
1307 #define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\ argument
1308 0, 1, 131072, g, 70, 512, 172, 0, 1, 4)
1383 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\ argument
1384 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
1387 #define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\ argument
1388 0, 1, 131072, g, 70, 512, 200, r, 6, 4)
1390 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1)
1403 #define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\ argument
1404 0, 1, 131072, g, 70, 512, 224, r, 6, 4)
1436 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1)
1450 0, 1, 166912, 0, 1, 756, 0, r, 3, 4)
1460 0, 1, 166912, 0, 1, 756, 256, r, 64, 4)
1480 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1)
1494 0, 1, 166912, 0, 1, 756, 512, r, 32, 4)
1504 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4)
1566 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1)
1580 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4)
1584 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
1588 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4)
1598 0, 1, 566024, 0, 1, 700, 672, r, 3, 4)
1607 #define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\ argument
1608 0, 1, 0, g, 4096, 128, 56, 0, 1, 4)
1617 #define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\ argument
1618 0, 1, 0, g, 4096, 128, 100, 0, 1, 4)
1628 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4)
1637 #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\ argument
1638 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
1682 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1)
1695 #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\ argument
1696 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
1699 #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\ argument
1700 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
1703 #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\ argument
1704 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
1713 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1714 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
1717 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1718 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
1721 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1722 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
1725 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ argument
1726 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
1729 #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1730 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
1733 #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1734 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
1737 #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1738 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
1741 #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1742 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
1745 #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1746 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
1749 #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1750 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
1753 #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1754 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
1757 #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ argument
1758 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
1761 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1762 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
1765 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1766 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
1769 #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1770 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
1773 #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ argument
1774 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
1777 #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
1778 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
1781 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
1782 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
1785 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
1786 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
1789 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
1790 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
1793 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
1794 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
1797 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
1798 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
1801 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
1802 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
1805 #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\ argument
1806 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
1809 #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1810 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
1813 #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1814 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
1817 #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1818 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
1821 #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1822 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
1825 #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1826 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
1829 #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1830 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
1833 #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
1834 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
1837 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
1838 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
1841 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
1842 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
1845 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
1846 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
1849 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
1850 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
1853 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
1854 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
1857 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
1858 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
1861 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ argument
1862 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
1865 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1866 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
1869 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1870 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
1873 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1874 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
1877 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1878 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
1881 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1882 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
1885 #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1886 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
1889 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ argument
1890 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
1893 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1894 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
1897 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1898 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
1901 #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1902 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
1905 #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1906 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
1909 #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1910 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
1913 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1914 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
1917 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1918 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
1921 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ argument
1922 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
1925 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1926 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
1929 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1930 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
1933 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1934 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
1937 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ argument
1938 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
1941 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
1942 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
1945 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
1946 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
1949 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
1950 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
1953 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
1954 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
1957 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
1958 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
1961 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
1962 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
1965 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
1966 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
1969 #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1970 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
1973 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1974 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
1977 #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1978 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
1981 #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1982 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
1985 #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1986 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
1989 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
1990 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
1993 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
1994 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
1997 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
1998 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
2001 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
2002 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
2005 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
2006 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
2009 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
2010 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
2013 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
2014 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
2017 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ argument
2018 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
2021 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\ argument
2022 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
2025 #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\ argument
2026 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
2029 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\ argument
2030 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
2033 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\ argument
2034 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
2037 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\ argument
2038 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
2041 #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\ argument
2042 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
2045 #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\ argument
2046 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
2049 #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\ argument
2050 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
2053 #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\ argument
2054 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
2057 #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\ argument
2058 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
2061 #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\ argument
2062 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
2065 #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\ argument
2066 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
2069 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2070 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
2079 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2080 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
2089 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2090 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
2099 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2100 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
2109 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2110 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
2119 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2120 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
2129 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2130 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
2139 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2140 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
2149 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\ argument
2150 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
2154 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4)
2164 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4)
2220 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1)
2234 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4)
2236 #define ASM_RAM_INIT_RAM_INIT BIT(1)
2250 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
2290 0, 1, 0, 0, 1, 204, 176, 0, 1, 4)
2358 #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1)
2372 t, 12, 0, 0, 1, 60, 0, 0, 1, 4)
2388 t, 12, 0, 0, 1, 60, 8, 0, 1, 4)
2404 t, 12, 0, 0, 1, 60, 12, 0, 1, 4)
2406 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0)
2414 t, 12, 0, 0, 1, 60, 16, r, 3, 4)
2430 t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
2476 t, 12, 0, 0, 1, 60, 48, 0, 1, 4)
2496 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
2510 t, 12, 436, 0, 1, 52, 0, 0, 1, 4)
2568 t, 12, 488, 0, 1, 32, 0, 0, 1, 4)
2578 t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
2594 t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
2610 t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
2656 t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
2714 t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
2724 t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
2746 t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
2798 t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
2814 t, 65, 52, 0, 1, 36, 4, 0, 1, 4)
2836 t, 65, 52, 0, 1, 36, 8, 0, 1, 4)
2846 t, 65, 52, 0, 1, 36, 12, 0, 1, 4)
2860 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
2874 t, 65, 52, 0, 1, 36, 16, 0, 1, 4)
2890 t, 65, 52, 0, 1, 36, 20, 0, 1, 4)
2900 t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
2928 t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
2962 t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
2970 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
2984 t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
2992 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1)
3006 t, 65, 88, 0, 1, 68, 8, 0, 1, 4)
3028 t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
3042 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
3056 t, 65, 88, 0, 1, 68, 20, 0, 1, 4)
3064 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
3078 t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
3106 t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
3134 t, 65, 88, 0, 1, 68, 48, 0, 1, 4)
3150 t, 65, 164, 0, 1, 4, 0, 0, 1, 4)
3218 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
3232 t, 65, 168, 0, 1, 4, 0, 0, 1, 4)
3270 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
3284 t, 13, 0, 0, 1, 60, 0, 0, 1, 4)
3300 t, 13, 0, 0, 1, 60, 8, 0, 1, 4)
3316 t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
3362 t, 13, 60, 0, 1, 312, 0, 0, 1, 4)
3366 t, 13, 60, 0, 1, 312, 4, 0, 1, 4)
3370 t, 13, 60, 0, 1, 312, 8, 0, 1, 4)
3374 t, 13, 60, 0, 1, 312, 12, 0, 1, 4)
3378 t, 13, 60, 0, 1, 312, 16, 0, 1, 4)
3382 t, 13, 60, 0, 1, 312, 20, 0, 1, 4)
3386 t, 13, 60, 0, 1, 312, 24, 0, 1, 4)
3390 t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
3394 t, 13, 60, 0, 1, 312, 32, 0, 1, 4)
3398 t, 13, 60, 0, 1, 312, 36, 0, 1, 4)
3402 t, 13, 60, 0, 1, 312, 40, 0, 1, 4)
3406 t, 13, 60, 0, 1, 312, 44, 0, 1, 4)
3410 t, 13, 60, 0, 1, 312, 48, 0, 1, 4)
3414 t, 13, 60, 0, 1, 312, 52, 0, 1, 4)
3418 t, 13, 60, 0, 1, 312, 56, 0, 1, 4)
3422 t, 13, 60, 0, 1, 312, 60, 0, 1, 4)
3426 t, 13, 60, 0, 1, 312, 64, 0, 1, 4)
3430 t, 13, 60, 0, 1, 312, 68, 0, 1, 4)
3434 t, 13, 60, 0, 1, 312, 72, 0, 1, 4)
3438 t, 13, 60, 0, 1, 312, 76, 0, 1, 4)
3442 t, 13, 60, 0, 1, 312, 80, 0, 1, 4)
3446 t, 13, 60, 0, 1, 312, 84, 0, 1, 4)
3450 t, 13, 60, 0, 1, 312, 88, 0, 1, 4)
3454 t, 13, 60, 0, 1, 312, 92, 0, 1, 4)
3458 t, 13, 60, 0, 1, 312, 96, 0, 1, 4)
3462 t, 13, 60, 0, 1, 312, 100, 0, 1, 4)
3466 t, 13, 60, 0, 1, 312, 104, 0, 1, 4)
3470 t, 13, 60, 0, 1, 312, 108, 0, 1, 4)
3474 t, 13, 60, 0, 1, 312, 112, 0, 1, 4)
3478 t, 13, 60, 0, 1, 312, 116, 0, 1, 4)
3482 t, 13, 60, 0, 1, 312, 120, 0, 1, 4)
3486 t, 13, 60, 0, 1, 312, 124, 0, 1, 4)
3490 t, 13, 60, 0, 1, 312, 128, 0, 1, 4)
3494 t, 13, 60, 0, 1, 312, 132, 0, 1, 4)
3498 t, 13, 60, 0, 1, 312, 136, 0, 1, 4)
3502 t, 13, 60, 0, 1, 312, 140, 0, 1, 4)
3506 t, 13, 60, 0, 1, 312, 144, 0, 1, 4)
3510 t, 13, 60, 0, 1, 312, 148, 0, 1, 4)
3514 t, 13, 60, 0, 1, 312, 152, 0, 1, 4)
3518 t, 13, 60, 0, 1, 312, 156, 0, 1, 4)
3522 t, 13, 60, 0, 1, 312, 160, 0, 1, 4)
3526 t, 13, 60, 0, 1, 312, 164, 0, 1, 4)
3530 t, 13, 60, 0, 1, 312, 168, 0, 1, 4)
3534 t, 13, 60, 0, 1, 312, 172, 0, 1, 4)
3538 t, 13, 60, 0, 1, 312, 176, 0, 1, 4)
3542 t, 13, 60, 0, 1, 312, 180, 0, 1, 4)
3546 t, 13, 60, 0, 1, 312, 184, 0, 1, 4)
3550 t, 13, 60, 0, 1, 312, 188, 0, 1, 4)
3554 t, 13, 60, 0, 1, 312, 192, 0, 1, 4)
3558 t, 13, 60, 0, 1, 312, 196, 0, 1, 4)
3562 t, 13, 60, 0, 1, 312, 200, 0, 1, 4)
3566 t, 13, 60, 0, 1, 312, 204, 0, 1, 4)
3570 t, 13, 60, 0, 1, 312, 208, 0, 1, 4)
3574 t, 13, 60, 0, 1, 312, 212, 0, 1, 4)
3578 t, 13, 60, 0, 1, 312, 216, 0, 1, 4)
3582 t, 13, 60, 0, 1, 312, 220, 0, 1, 4)
3586 t, 13, 60, 0, 1, 312, 224, 0, 1, 4)
3590 t, 13, 60, 0, 1, 312, 228, 0, 1, 4)
3594 t, 13, 60, 0, 1, 312, 232, 0, 1, 4)
3598 t, 13, 60, 0, 1, 312, 236, 0, 1, 4)
3602 t, 13, 60, 0, 1, 312, 240, 0, 1, 4)
3606 t, 13, 60, 0, 1, 312, 244, 0, 1, 4)
3610 t, 13, 60, 0, 1, 312, 248, 0, 1, 4)
3614 t, 13, 60, 0, 1, 312, 252, 0, 1, 4)
3618 t, 13, 60, 0, 1, 312, 256, 0, 1, 4)
3622 t, 13, 60, 0, 1, 312, 260, 0, 1, 4)
3626 t, 13, 60, 0, 1, 312, 264, 0, 1, 4)
3630 t, 13, 60, 0, 1, 312, 268, 0, 1, 4)
3634 t, 13, 60, 0, 1, 312, 272, 0, 1, 4)
3638 t, 13, 60, 0, 1, 312, 276, 0, 1, 4)
3642 t, 13, 60, 0, 1, 312, 280, 0, 1, 4)
3646 t, 13, 60, 0, 1, 312, 284, 0, 1, 4)
3650 t, 13, 60, 0, 1, 312, 288, 0, 1, 4)
3654 t, 13, 60, 0, 1, 312, 292, 0, 1, 4)
3658 t, 13, 60, 0, 1, 312, 296, 0, 1, 4)
3662 t, 13, 60, 0, 1, 312, 300, 0, 1, 4)
3666 t, 13, 60, 0, 1, 312, 304, 0, 1, 4)
3670 t, 13, 60, 0, 1, 312, 308, 0, 1, 4)
3674 t, 13, 372, 0, 1, 64, 0, 0, 1, 4)
3678 t, 13, 372, 0, 1, 64, 4, 0, 1, 4)
3688 t, 13, 372, 0, 1, 64, 8, 0, 1, 4)
3692 t, 13, 372, 0, 1, 64, 12, 0, 1, 4)
3702 t, 13, 372, 0, 1, 64, 16, 0, 1, 4)
3706 t, 13, 372, 0, 1, 64, 20, 0, 1, 4)
3716 t, 13, 372, 0, 1, 64, 24, 0, 1, 4)
3720 t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
3730 t, 13, 372, 0, 1, 64, 32, 0, 1, 4)
3734 t, 13, 372, 0, 1, 64, 36, 0, 1, 4)
3744 t, 13, 372, 0, 1, 64, 40, 0, 1, 4)
3748 t, 13, 372, 0, 1, 64, 44, 0, 1, 4)
3758 t, 13, 372, 0, 1, 64, 48, 0, 1, 4)
3762 t, 13, 372, 0, 1, 64, 52, 0, 1, 4)
3772 t, 13, 372, 0, 1, 64, 56, 0, 1, 4)
3776 t, 13, 372, 0, 1, 64, 60, 0, 1, 4)
3786 t, 13, 436, 0, 1, 52, 0, 0, 1, 4)
3844 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
3846 #define DSM_RAM_INIT_RAM_INIT BIT(1)
3860 0, 1, 20, 0, 1, 3528, 0, r, 67, 4)
3888 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4)
3902 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1)
3916 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4)
3918 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1)
3932 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4)
3946 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1)
3960 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4)
3970 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4)
3980 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
4000 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)
4013 #define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\ argument
4014 0, 1, 149504, g, 138, 8, 0, r, 2, 4)
4028 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1)
4041 #define EACL_ES2_CNT(g) __REG(TARGET_EACL,\ argument
4042 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4)
4046 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4)
4072 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1)
4086 0, 1, 118696, 0, 1, 8, 0, r, 2, 4)
4124 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1)
4138 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4)
4140 #define EACL_RAM_INIT_RAM_INIT BIT(1)
4154 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
4164 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
4174 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
4184 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
4188 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
4192 0, 1, 8, 0, 1, 428, 116, r, 8, 4)
4196 0, 1, 8, 0, 1, 428, 148, r, 8, 4)
4200 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
4220 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1)
4234 0, 1, 8, 0, 1, 428, 256, r, 8, 4)
4244 0, 1, 8, 0, 1, 428, 364, 0, 1, 4)
4260 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
4280 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1)
4294 0, 1, 8, 0, 1, 428, 384, 0, 1, 4)
4304 0, 1, 8, 0, 1, 428, 388, 0, 1, 4)
4314 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
4324 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
4334 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
4350 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
4402 0, 1, 8, 0, 1, 428, 416, 0, 1, 4)
4404 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0)
4412 0, 1, 8, 0, 1, 428, 424, 0, 1, 4)
4422 0, 1, 0, 0, 1, 424, 0, 0, 1, 4)
4436 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1)
4450 0, 1, 0, 0, 1, 424, 8, 0, 1, 4)
4458 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1)
4472 0, 1, 0, 0, 1, 424, 20, 0, 1, 4)
4474 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1)
4488 0, 1, 0, 0, 1, 424, 24, r, 65, 4)
4497 #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\ argument
4498 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
4513 #define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\ argument
4514 0, 1, 0, g, 5040, 32, 0, 0, 1, 4)
4529 #define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\ argument
4530 0, 1, 0, g, 5040, 32, 4, 0, 1, 4)
4545 #define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\ argument
4546 0, 1, 0, g, 5040, 32, 8, 0, 1, 4)
4566 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1)
4579 #define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\ argument
4580 0, 1, 0, g, 5040, 32, 12, 0, 1, 4)
4589 #define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\ argument
4590 0, 1, 0, g, 5040, 32, 16, 0, 1, 4)
4610 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1)
4623 #define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\ argument
4624 0, 1, 162816, g, 72, 4, 0, 0, 1, 4)
4640 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4)
4662 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4)
4671 #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\ argument
4672 0, 1, 161664, g, 4, 32, 0, r, 4, 4)
4681 #define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\ argument
4682 0, 1, 161664, g, 4, 32, 16, r, 4, 4)
4684 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1)
4698 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4)
4744 0, 1, 184000, 0, 1, 312, 8, r, 70, 4)
4764 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1)
4778 0, 1, 184000, 0, 1, 312, 288, r, 5, 4)
4788 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4)
4798 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4)
4808 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
4828 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)
4842 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
4858 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
4862 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
4938 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
4948 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
5028 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1)
5042 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
5058 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
5074 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
5106 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
5120 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
5136 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
5200 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
5216 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
5220 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
5236 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
5240 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
5244 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
5246 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
5260 t, 12, 0, 0, 1, 56, 0, 0, 1, 4)
5336 t, 12, 0, 0, 1, 56, 4, 0, 1, 4)
5358 t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
5434 t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
5456 t, 13, 0, 0, 1, 56, 0, 0, 1, 4)
5532 t, 13, 0, 0, 1, 56, 4, 0, 1, 4)
5554 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
5562 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1)
5636 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
5644 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1)
5712 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
5720 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1)
5764 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
5772 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1)
5839 #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\ argument
5840 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
5878 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1)
5886 0, 1, 320, 0, 1, 16, 0, 0, 1, 4)
5896 0, 1, 320, 0, 1, 16, 4, 0, 1, 4)
5906 0, 1, 320, 0, 1, 16, 8, 0, 1, 4)
5916 0, 1, 320, 0, 1, 16, 12, 0, 1, 4)
5943 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\ argument
5944 0, 1, 336, g, 3, 28, 0, r, 2, 4)
5947 #define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\ argument
5948 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
5957 #define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\ argument
5958 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
5967 #define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\ argument
5968 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
5971 #define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\ argument
5972 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
5981 #define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\ argument
5982 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
5985 #define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\ argument
5986 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
6043 #define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\ argument
6044 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
6053 #define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\ argument
6054 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
6057 #define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\ argument
6058 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
6067 #define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\ argument
6068 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
6077 #define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\ argument
6078 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
6081 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ argument
6082 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
6091 #define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ argument
6092 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
6101 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\ argument
6102 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
6117 #define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\ argument
6118 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
6145 #define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\ argument
6146 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
6150 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
6194 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1)
6207 #define QRES_RES_CFG(g) __REG(TARGET_QRES,\ argument
6208 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
6217 #define QRES_RES_STAT(g) __REG(TARGET_QRES,\ argument
6218 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
6227 #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\ argument
6228 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
6238 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
6246 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
6260 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
6264 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
6266 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
6274 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
6276 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0)
6284 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
6300 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
6304 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
6338 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
6352 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0)
6360 0, 1, 544, 0, 1, 1128, 0, r, 70, 4)
6374 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1)
6388 0, 1, 544, 0, 1, 1128, 284, r, 70, 4)
6398 0, 1, 544, 0, 1, 1128, 564, r, 70, 4)
6400 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1)
6414 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4)
6424 0, 1, 2304, 0, 1, 40, 0, r, 7, 4)
6434 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4)
6442 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1)
6456 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4)
6458 #define QSYS_RAM_INIT_RAM_INIT BIT(1)
6472 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4)
6482 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4)
6490 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1)
6504 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4)
6530 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1)
6543 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\ argument
6544 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
6565 #define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\ argument
6566 0, 1, 360448, g, 70, 256, 4, r, 8, 4)
6575 #define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\ argument
6576 0, 1, 360448, g, 70, 256, 36, r, 8, 4)
6585 #define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\ argument
6586 0, 1, 360448, g, 70, 256, 68, r, 8, 4)
6595 #define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\ argument
6596 0, 1, 360448, g, 70, 256, 100, r, 8, 4)
6605 #define REW_TAG_CTRL(g) __REG(TARGET_REW,\ argument
6606 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
6645 #define REW_DSCP_MAP(g) __REG(TARGET_REW,\ argument
6646 0, 1, 360448, g, 70, 256, 136, 0, 1, 4)
6648 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1)
6662 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
6688 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
6702 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
6712 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
6722 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
6726 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
6730 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
6740 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
6748 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0)
6756 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
6758 #define REW_RAM_INIT_RAM_INIT BIT(1)
6772 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
6810 #define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1)
6824 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
6840 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
6844 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
6848 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
6852 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
6856 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
6860 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
6864 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
6874 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
6884 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
6894 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
6898 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
6902 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
6906 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
6910 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
6914 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
6918 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
6922 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
6926 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
6930 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
6934 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
6972 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1)
6986 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7002 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7006 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7010 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7014 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7018 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7022 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7026 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7036 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7046 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7056 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7060 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7064 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7068 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7072 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7076 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7080 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7084 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7088 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7092 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7096 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7134 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1)
7148 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7164 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7168 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7172 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7176 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7180 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7184 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7188 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7198 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7208 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7212 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7216 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7220 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7224 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7228 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7232 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7236 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7240 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7244 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7248 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
7250 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1)
7264 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4)
7266 #define VOP_RAM_INIT_RAM_INIT BIT(1)
7280 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4)
7307 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\ argument
7308 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
7317 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\ argument
7318 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
7327 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\ argument
7328 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
7337 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\ argument
7338 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
7347 #define XQS_CNT(g) __REG(TARGET_XQS,\ argument
7348 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)