116 	spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5,  in sparx5_fdma_rx_activate()
118 	spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id));  in sparx5_fdma_rx_activate()
121 	spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_RX_DCB_MAX_DBS) |  in sparx5_fdma_rx_activate()
141 	spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE);  in sparx5_fdma_rx_activate()
162 	spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5,  in sparx5_fdma_tx_activate()
164 	spx5_wr(((u64)tx->dma) >> 32, sparx5, FDMA_DCB_LLP1(tx->channel_id));  in sparx5_fdma_tx_activate()
167 	spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_TX_DCB_MAX_DBS) |  in sparx5_fdma_tx_activate()
177 	spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_ACTIVATE);  in sparx5_fdma_tx_activate()
190 	spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD);  in sparx5_fdma_rx_reload()
196 	spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_RELOAD);  in sparx5_fdma_tx_reload()
471 		spx5_wr(0, sparx5, FDMA_INTR_DB_ENA);  in sparx5_fdma_handler()
472 		spx5_wr(db, sparx5, FDMA_INTR_DB);  in sparx5_fdma_handler()
481 		spx5_wr(err, sparx5, FDMA_INTR_ERR);  in sparx5_fdma_handler()
482 		spx5_wr(err_type, sparx5, FDMA_ERRORS);  in sparx5_fdma_handler()
494 	spx5_wr(QS_XTR_GRP_CFG_MODE_SET(2) |  in sparx5_fdma_injection_mode()
498 	spx5_wr(QS_INJ_GRP_CFG_MODE_SET(2) |  in sparx5_fdma_injection_mode()
505 		spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) |  in sparx5_fdma_injection_mode()
552 	spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL);  in sparx5_fdma_start()
553 	spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL);  in sparx5_fdma_start()