Lines Matching refs:ECON1
201 if (addr >= EIE && addr <= ECON1) in enc28j60_set_bank()
207 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, in enc28j60_set_bank()
210 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, in enc28j60_set_bank()
215 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, in enc28j60_set_bank()
218 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, in enc28j60_set_bank()
544 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2), in enc28j60_dump_regs()
635 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); in enc28j60_lowpower()
637 poll_ready(priv, ECON1, ECON1_TXRTS, 0); in enc28j60_lowpower()
661 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00); in enc28j60_hw_init()
761 nolock_reg_bfset(priv, ECON1, ECON1_RXEN); in enc28j60_hw_enable()
771 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); in enc28j60_hw_disable()
921 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); in enc28j60_hw_rx()
922 nolock_reg_bfset(priv, ECON1, ECON1_RXRST); in enc28j60_hw_rx()
923 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST); in enc28j60_hw_rx()
926 nolock_reg_bfset(priv, ECON1, ECON1_RXEN); in enc28j60_hw_rx()
1085 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); in enc28j60_tx_clear()
1180 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); in enc28j60_irq()
1186 nolock_reg_bfset(priv, ECON1, ECON1_TXRST); in enc28j60_irq()
1187 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST); in enc28j60_irq()
1197 locked_reg_bfset(priv, ECON1, in enc28j60_irq()
1278 locked_reg_bfset(priv, ECON1, ECON1_TXRTS); in enc28j60_hw_tx()