Lines Matching refs:mdev
12 static u8 mlx5e_mpwrq_min_page_shift(struct mlx5_core_dev *mdev) in mlx5e_mpwrq_min_page_shift() argument
14 u8 min_page_shift = MLX5_CAP_GEN_2(mdev, log_min_mkey_entity_size); in mlx5e_mpwrq_min_page_shift()
19 u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *xsk) in mlx5e_mpwrq_page_shift() argument
22 u8 min_page_shift = mlx5e_mpwrq_min_page_shift(mdev); in mlx5e_mpwrq_page_shift()
32 mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *xsk) in mlx5e_mpwrq_umr_mode() argument
43 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_mpwrq_umr_mode()
101 u8 mlx5e_mpwrq_log_wqe_sz(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_log_wqe_sz() argument
109 max_wqe_size = mlx5e_get_max_sq_aligned_wqebbs(mdev) * MLX5_SEND_WQE_BB; in mlx5e_mpwrq_log_wqe_sz()
119 u8 mlx5e_mpwrq_pages_per_wqe(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_pages_per_wqe() argument
122 u8 log_wqe_sz = mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); in mlx5e_mpwrq_pages_per_wqe()
142 u16 mlx5e_mpwrq_umr_wqe_sz(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_umr_wqe_sz() argument
145 u8 pages_per_wqe = mlx5e_mpwrq_pages_per_wqe(mdev, page_shift, umr_mode); in mlx5e_mpwrq_umr_wqe_sz()
157 u8 mlx5e_mpwrq_umr_wqebbs(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_umr_wqebbs() argument
160 return DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(mdev, page_shift, umr_mode), in mlx5e_mpwrq_umr_wqebbs()
164 u8 mlx5e_mpwrq_mtts_per_wqe(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_mtts_per_wqe() argument
167 u8 pages_per_wqe = mlx5e_mpwrq_pages_per_wqe(mdev, page_shift, umr_mode); in mlx5e_mpwrq_mtts_per_wqe()
178 u32 mlx5e_mpwrq_max_num_entries(struct mlx5_core_dev *mdev, in mlx5e_mpwrq_max_num_entries() argument
183 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size)); in mlx5e_mpwrq_max_num_entries()
201 static u8 mlx5e_mpwrq_max_log_rq_size(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_max_log_rq_size() argument
204 u8 mtts_per_wqe = mlx5e_mpwrq_mtts_per_wqe(mdev, page_shift, umr_mode); in mlx5e_mpwrq_max_log_rq_size()
205 u32 max_entries = mlx5e_mpwrq_max_num_entries(mdev, umr_mode); in mlx5e_mpwrq_max_log_rq_size()
210 u8 mlx5e_mpwrq_max_log_rq_pkts(struct mlx5_core_dev *mdev, u8 page_shift, in mlx5e_mpwrq_max_log_rq_pkts() argument
213 return mlx5e_mpwrq_max_log_rq_size(mdev, page_shift, umr_mode) + in mlx5e_mpwrq_max_log_rq_pkts()
214 mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode) - in mlx5e_mpwrq_max_log_rq_pkts()
252 static u32 mlx5e_rx_get_linear_stride_sz(struct mlx5_core_dev *mdev, in mlx5e_rx_get_linear_stride_sz() argument
263 return mpwqe ? 1 << mlx5e_mpwrq_page_shift(mdev, xsk) : PAGE_SIZE; in mlx5e_rx_get_linear_stride_sz()
273 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5_core_dev *mdev, in mlx5e_mpwqe_log_pkts_per_wqe() argument
277 u32 linear_stride_sz = mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, true); in mlx5e_mpwqe_log_pkts_per_wqe()
278 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_mpwqe_log_pkts_per_wqe()
279 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_mpwqe_log_pkts_per_wqe()
281 return mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode) - in mlx5e_mpwqe_log_pkts_per_wqe()
285 bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev, in mlx5e_rx_is_linear_skb() argument
305 static bool mlx5e_verify_rx_mpwqe_strides(struct mlx5_core_dev *mdev, in mlx5e_verify_rx_mpwqe_strides() argument
311 mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode)) in mlx5e_verify_rx_mpwqe_strides()
321 if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) in mlx5e_verify_rx_mpwqe_strides()
327 bool mlx5e_verify_params_rx_mpwqe_strides(struct mlx5_core_dev *mdev, in mlx5e_verify_params_rx_mpwqe_strides() argument
331 u8 log_wqe_num_of_strides = mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); in mlx5e_verify_params_rx_mpwqe_strides()
332 u8 log_wqe_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); in mlx5e_verify_params_rx_mpwqe_strides()
333 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_verify_params_rx_mpwqe_strides()
334 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_verify_params_rx_mpwqe_strides()
336 return mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, in mlx5e_verify_params_rx_mpwqe_strides()
341 bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, in mlx5e_rx_mpwqe_is_linear_skb() argument
345 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_rx_mpwqe_is_linear_skb()
346 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_rx_mpwqe_is_linear_skb()
351 if (!mlx5e_rx_is_linear_skb(mdev, params, xsk)) in mlx5e_rx_mpwqe_is_linear_skb()
354 log_stride_sz = order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, true)); in mlx5e_rx_mpwqe_is_linear_skb()
355 log_wqe_sz = mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); in mlx5e_rx_mpwqe_is_linear_skb()
362 return mlx5e_verify_rx_mpwqe_strides(mdev, log_stride_sz, in mlx5e_rx_mpwqe_is_linear_skb()
367 u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev, in mlx5e_mpwqe_get_log_rq_size() argument
371 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_mpwqe_get_log_rq_size()
374 log_pkts_per_wqe = mlx5e_mpwqe_log_pkts_per_wqe(mdev, params, xsk); in mlx5e_mpwqe_get_log_rq_size()
375 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_mpwqe_get_log_rq_size()
376 max_log_rq_size = mlx5e_mpwrq_max_log_rq_size(mdev, page_shift, umr_mode); in mlx5e_mpwqe_get_log_rq_size()
395 u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, in mlx5e_shampo_get_log_hd_entry_size() argument
401 u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, in mlx5e_shampo_get_log_rsrv_size() argument
407 u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, in mlx5e_shampo_get_log_pkt_per_rsrv() argument
410 u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * in mlx5e_shampo_get_log_pkt_per_rsrv()
416 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, in mlx5e_mpwqe_get_log_stride_size() argument
420 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) in mlx5e_mpwqe_get_log_stride_size()
421 return order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, true)); in mlx5e_mpwqe_get_log_stride_size()
427 return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev); in mlx5e_mpwqe_get_log_stride_size()
430 u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, in mlx5e_mpwqe_get_log_num_strides() argument
434 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_mpwqe_get_log_num_strides()
435 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_mpwqe_get_log_num_strides()
438 log_wqe_size = mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); in mlx5e_mpwqe_get_log_num_strides()
439 log_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); in mlx5e_mpwqe_get_log_num_strides()
452 u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, in mlx5e_get_rq_headroom() argument
461 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) in mlx5e_get_rq_headroom()
470 u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *params) in mlx5e_calc_sq_stop_room() argument
475 stop_room = mlx5e_ktls_get_stop_room(mdev, params); in mlx5e_calc_sq_stop_room()
476 stop_room += mlx5e_stop_room_for_max_wqe(mdev); in mlx5e_calc_sq_stop_room()
482 stop_room += mlx5e_stop_room_for_mpwqe(mdev); in mlx5e_calc_sq_stop_room()
487 int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params) in mlx5e_validate_params() argument
492 stop_room = mlx5e_calc_sq_stop_room(mdev, params); in mlx5e_validate_params()
494 mlx5_core_err(mdev, "Stop room %u is bigger than the SQ size %zu\n", in mlx5e_validate_params()
573 bool slow_pci_heuristic(struct mlx5_core_dev *mdev) in slow_pci_heuristic() argument
578 mlx5_port_max_linkspeed(mdev, &link_speed); in slow_pci_heuristic()
579 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); in slow_pci_heuristic()
580 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", in slow_pci_heuristic()
589 int mlx5e_mpwrq_validate_regular(struct mlx5_core_dev *mdev, struct mlx5e_params *params) in mlx5e_mpwrq_validate_regular() argument
591 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, NULL); in mlx5e_mpwrq_validate_regular()
592 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, NULL); in mlx5e_mpwrq_validate_regular()
594 if (!mlx5e_check_fragmented_striding_rq_cap(mdev, page_shift, umr_mode)) in mlx5e_mpwrq_validate_regular()
600 int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev, struct mlx5e_params *params, in mlx5e_mpwrq_validate_xsk() argument
603 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_mpwrq_validate_xsk()
604 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_mpwrq_validate_xsk()
607 if (!mlx5e_check_fragmented_striding_rq_cap(mdev, page_shift, umr_mode)) { in mlx5e_mpwrq_validate_xsk()
608 mlx5_core_err(mdev, "Striding RQ for XSK can't be activated with page_shift %u and umr_mode %d\n", in mlx5e_mpwrq_validate_xsk()
613 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) { in mlx5e_mpwrq_validate_xsk()
614 mlx5_core_err(mdev, "Striding RQ linear mode for XSK can't be activated with current params\n"); in mlx5e_mpwrq_validate_xsk()
622 mlx5e_mpwrq_max_log_rq_pkts(mdev, page_shift, xsk->unaligned)); in mlx5e_mpwrq_validate_xsk()
624 mlx5_core_err(mdev, "Current RQ length %d is too big for XSK with given frame size %u\n", in mlx5e_mpwrq_validate_xsk()
632 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, in mlx5e_init_rq_type_params() argument
640 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) in mlx5e_set_rq_type() argument
647 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, in mlx5e_build_rq_params() argument
658 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) && in mlx5e_build_rq_params()
659 !mlx5e_mpwrq_validate_regular(mdev, params) && in mlx5e_build_rq_params()
660 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) || in mlx5e_build_rq_params()
661 !mlx5e_rx_is_linear_skb(mdev, params, NULL))) in mlx5e_build_rq_params()
663 mlx5e_set_rq_type(mdev, params); in mlx5e_build_rq_params()
664 mlx5e_init_rq_type_params(mdev, params); in mlx5e_build_rq_params()
733 static int mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, in mlx5e_build_rq_frags_info() argument
747 if (mlx5e_rx_is_linear_skb(mdev, params, xsk)) { in mlx5e_build_rq_frags_info()
750 frag_stride = mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, false); in mlx5e_build_rq_frags_info()
778 mlx5_core_err(mdev, "MTU %u is too big for non-linear legacy RQ (max %d)\n", in mlx5e_build_rq_frags_info()
845 mlx5_core_dbg(mdev, "%s: wqe_bulk = %u, wqe_bulk_refill_unit = %u\n", in mlx5e_build_rq_frags_info()
870 static void mlx5e_build_common_cq_param(struct mlx5_core_dev *mdev, in mlx5e_build_common_cq_param() argument
875 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); in mlx5e_build_common_cq_param()
876 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) in mlx5e_build_common_cq_param()
880 static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, in mlx5e_shampo_get_log_cq_size() argument
884 int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; in mlx5e_shampo_get_log_cq_size()
885 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); in mlx5e_shampo_get_log_cq_size()
886 int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); in mlx5e_shampo_get_log_cq_size()
887 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); in mlx5e_shampo_get_log_cq_size()
888 int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); in mlx5e_shampo_get_log_cq_size()
897 static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, in mlx5e_build_rx_cq_param() argument
908 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index); in mlx5e_build_rx_cq_param()
910 log_cq_size = mlx5e_shampo_get_log_cq_size(mdev, params, xsk); in mlx5e_build_rx_cq_param()
912 log_cq_size = mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk) + in mlx5e_build_rx_cq_param()
913 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); in mlx5e_build_rx_cq_param()
924 MLX5_CAP_GEN(mdev, enhanced_cqe_compression) ? in mlx5e_build_rx_cq_param()
930 mlx5e_build_common_cq_param(mdev, param); in mlx5e_build_rx_cq_param()
934 static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params) in rq_end_pad_mode() argument
937 bool ro = MLX5_CAP_GEN(mdev, relaxed_ordering_write); in rq_end_pad_mode()
943 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, in mlx5e_build_rq_param() argument
956 u8 log_wqe_num_of_strides = mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); in mlx5e_build_rq_param()
957 u8 log_wqe_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); in mlx5e_build_rq_param()
958 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_build_rq_param()
959 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_build_rq_param()
961 if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, in mlx5e_build_rq_param()
964 mlx5_core_err(mdev, in mlx5e_build_rq_param()
975 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); in mlx5e_build_rq_param()
979 mlx5e_shampo_get_log_rsrv_size(mdev, params)); in mlx5e_build_rq_param()
982 mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); in mlx5e_build_rq_param()
984 mlx5e_shampo_get_log_hd_entry_size(mdev, params)); in mlx5e_build_rq_param()
996 err = mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info, in mlx5e_build_rq_param()
1004 MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params)); in mlx5e_build_rq_param()
1007 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); in mlx5e_build_rq_param()
1012 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); in mlx5e_build_rq_param()
1013 mlx5e_build_rx_cq_param(mdev, params, xsk, ¶m->cqp); in mlx5e_build_rq_param()
1018 void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev, in mlx5e_build_drop_rq_param() argument
1030 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); in mlx5e_build_drop_rq_param()
1033 void mlx5e_build_tx_cq_param(struct mlx5_core_dev *mdev, in mlx5e_build_tx_cq_param() argument
1041 mlx5e_build_common_cq_param(mdev, param); in mlx5e_build_tx_cq_param()
1045 void mlx5e_build_sq_param_common(struct mlx5_core_dev *mdev, in mlx5e_build_sq_param_common() argument
1052 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); in mlx5e_build_sq_param_common()
1054 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); in mlx5e_build_sq_param_common()
1057 void mlx5e_build_sq_param(struct mlx5_core_dev *mdev, in mlx5e_build_sq_param() argument
1065 allow_swp = mlx5_geneve_tx_allowed(mdev) || in mlx5e_build_sq_param()
1066 (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_CRYPTO); in mlx5e_build_sq_param()
1067 mlx5e_build_sq_param_common(mdev, param); in mlx5e_build_sq_param()
1071 param->stop_room = mlx5e_calc_sq_stop_room(mdev, params); in mlx5e_build_sq_param()
1072 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); in mlx5e_build_sq_param()
1075 static void mlx5e_build_ico_cq_param(struct mlx5_core_dev *mdev, in mlx5e_build_ico_cq_param() argument
1083 mlx5e_build_common_cq_param(mdev, param); in mlx5e_build_ico_cq_param()
1093 u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, in mlx5e_shampo_hd_per_wqe() argument
1097 int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; in mlx5e_shampo_hd_per_wqe()
1098 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL)); in mlx5e_shampo_hd_per_wqe()
1099 int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); in mlx5e_shampo_hd_per_wqe()
1100 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); in mlx5e_shampo_hd_per_wqe()
1106 mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n", in mlx5e_shampo_hd_per_wqe()
1115 u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev, in mlx5e_shampo_hd_per_wq() argument
1123 hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); in mlx5e_shampo_hd_per_wq()
1128 static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev, in mlx5e_shampo_icosq_sz() argument
1137 max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE(mdev); in mlx5e_shampo_icosq_sz()
1138 max_hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); in mlx5e_shampo_icosq_sz()
1148 static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5_core_dev *mdev, in mlx5e_mpwrq_total_umr_wqebbs() argument
1152 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); in mlx5e_mpwrq_total_umr_wqebbs()
1153 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); in mlx5e_mpwrq_total_umr_wqebbs()
1156 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode); in mlx5e_mpwrq_total_umr_wqebbs()
1158 return umr_wqebbs * (1 << mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); in mlx5e_mpwrq_total_umr_wqebbs()
1161 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, in mlx5e_build_icosq_log_wq_sz() argument
1172 wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, NULL); in mlx5e_build_icosq_log_wq_sz()
1198 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); in mlx5e_build_icosq_log_wq_sz()
1203 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); in mlx5e_build_icosq_log_wq_sz()
1208 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); in mlx5e_build_icosq_log_wq_sz()
1213 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); in mlx5e_build_icosq_log_wq_sz()
1220 wqebbs += mlx5e_shampo_icosq_sz(mdev, params, rqp); in mlx5e_build_icosq_log_wq_sz()
1230 useful_space = PAGE_SIZE - mlx5e_get_max_sq_wqebbs(mdev) + MLX5_SEND_WQE_BB; in mlx5e_build_icosq_log_wq_sz()
1237 static u8 mlx5e_build_async_icosq_log_wq_sz(struct mlx5_core_dev *mdev) in mlx5e_build_async_icosq_log_wq_sz() argument
1239 if (mlx5e_is_ktls_rx(mdev)) in mlx5e_build_async_icosq_log_wq_sz()
1245 static void mlx5e_build_icosq_param(struct mlx5_core_dev *mdev, in mlx5e_build_icosq_param() argument
1252 mlx5e_build_sq_param_common(mdev, param); in mlx5e_build_icosq_param()
1255 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); in mlx5e_build_icosq_param()
1256 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); in mlx5e_build_icosq_param()
1259 static void mlx5e_build_async_icosq_param(struct mlx5_core_dev *mdev, in mlx5e_build_async_icosq_param() argument
1266 mlx5e_build_sq_param_common(mdev, param); in mlx5e_build_async_icosq_param()
1267 param->stop_room = mlx5e_stop_room_for_wqe(mdev, 1); /* for XSK NOP */ in mlx5e_build_async_icosq_param()
1268 param->is_tls = mlx5e_is_ktls_rx(mdev); in mlx5e_build_async_icosq_param()
1270 param->stop_room += mlx5e_stop_room_for_wqe(mdev, 1); /* for TLS RX resync NOP */ in mlx5e_build_async_icosq_param()
1271 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); in mlx5e_build_async_icosq_param()
1273 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); in mlx5e_build_async_icosq_param()
1276 void mlx5e_build_xdpsq_param(struct mlx5_core_dev *mdev, in mlx5e_build_xdpsq_param() argument
1284 mlx5e_build_sq_param_common(mdev, param); in mlx5e_build_xdpsq_param()
1287 param->is_xdp_mb = !mlx5e_rx_is_linear_skb(mdev, params, xsk); in mlx5e_build_xdpsq_param()
1288 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); in mlx5e_build_xdpsq_param()
1291 int mlx5e_build_channel_param(struct mlx5_core_dev *mdev, in mlx5e_build_channel_param() argument
1299 err = mlx5e_build_rq_param(mdev, params, NULL, q_counter, &cparam->rq); in mlx5e_build_channel_param()
1303 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(mdev, params, &cparam->rq); in mlx5e_build_channel_param()
1304 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(mdev); in mlx5e_build_channel_param()
1306 mlx5e_build_sq_param(mdev, params, &cparam->txq_sq); in mlx5e_build_channel_param()
1307 mlx5e_build_xdpsq_param(mdev, params, NULL, &cparam->xdp_sq); in mlx5e_build_channel_param()
1308 mlx5e_build_icosq_param(mdev, icosq_log_wq_sz, &cparam->icosq); in mlx5e_build_channel_param()
1309 mlx5e_build_async_icosq_param(mdev, async_icosq_log_wq_sz, &cparam->async_icosq); in mlx5e_build_channel_param()