Lines Matching refs:field
209 u8 field; in mlx4_QUERY_FUNC() local
235 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); in mlx4_QUERY_FUNC()
236 func->bus = field & 0xf; in mlx4_QUERY_FUNC()
237 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); in mlx4_QUERY_FUNC()
238 func->device = field & 0xf1; in mlx4_QUERY_FUNC()
239 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); in mlx4_QUERY_FUNC()
240 func->function = field & 0x7; in mlx4_QUERY_FUNC()
241 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); in mlx4_QUERY_FUNC()
242 func->physical_function = field & 0xf; in mlx4_QUERY_FUNC()
247 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); in mlx4_QUERY_FUNC()
248 func->rsvd_uars = field & 0x0f; in mlx4_QUERY_FUNC()
332 u8 field, port; in mlx4_QUERY_FUNC_CAP_wrapper() local
406 field = vhcr->in_modifier - in mlx4_QUERY_FUNC_CAP_wrapper()
408 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
414 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; in mlx4_QUERY_FUNC_CAP_wrapper()
418 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; in mlx4_QUERY_FUNC_CAP_wrapper()
422 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
443 field = 0; in mlx4_QUERY_FUNC_CAP_wrapper()
445 field |= QUERY_FUNC_CAP_PHV_BIT; in mlx4_QUERY_FUNC_CAP_wrapper()
447 field |= QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE; in mlx4_QUERY_FUNC_CAP_wrapper()
448 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
459 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | in mlx4_QUERY_FUNC_CAP_wrapper()
462 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
464 field = min( in mlx4_QUERY_FUNC_CAP_wrapper()
467 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
472 field = 0; /* protected FMR support not available as yet */ in mlx4_QUERY_FUNC_CAP_wrapper()
473 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
544 u8 field, op_modifier; in mlx4_QUERY_FUNC_CAP() local
568 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); in mlx4_QUERY_FUNC_CAP()
569 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { in mlx4_QUERY_FUNC_CAP()
574 func_cap->flags = field; in mlx4_QUERY_FUNC_CAP()
577 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); in mlx4_QUERY_FUNC_CAP()
578 func_cap->num_ports = field; in mlx4_QUERY_FUNC_CAP()
670 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); in mlx4_QUERY_FUNC_CAP()
671 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { in mlx4_QUERY_FUNC_CAP()
678 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); in mlx4_QUERY_FUNC_CAP()
679 func_cap->physical_port = field; in mlx4_QUERY_FUNC_CAP()
729 u8 field; in mlx4_QUERY_DEV_CAP() local
845 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAP_CLOCK_TO_USER); in mlx4_QUERY_DEV_CAP()
846 dev_cap->map_clock_to_user = field & 0x80; in mlx4_QUERY_DEV_CAP()
847 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
848 dev_cap->reserved_qps = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
849 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
850 dev_cap->max_qps = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
851 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
852 dev_cap->reserved_srqs = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
853 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
854 dev_cap->max_srqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
855 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
856 dev_cap->max_cq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
857 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); in mlx4_QUERY_DEV_CAP()
858 dev_cap->reserved_cqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); in mlx4_QUERY_DEV_CAP()
860 dev_cap->max_cqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
861 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); in mlx4_QUERY_DEV_CAP()
862 dev_cap->max_mpts = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
863 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); in mlx4_QUERY_DEV_CAP()
864 dev_cap->reserved_eqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
865 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); in mlx4_QUERY_DEV_CAP()
866 dev_cap->max_eqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
867 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); in mlx4_QUERY_DEV_CAP()
868 dev_cap->reserved_mtts = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
869 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); in mlx4_QUERY_DEV_CAP()
870 dev_cap->reserved_mrws = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
873 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
874 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
875 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
876 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
877 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); in mlx4_QUERY_DEV_CAP()
878 field &= 0x1f; in mlx4_QUERY_DEV_CAP()
879 if (!field) in mlx4_QUERY_DEV_CAP()
882 dev_cap->max_gso_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
884 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); in mlx4_QUERY_DEV_CAP()
885 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
887 if (field & 0x10) in mlx4_QUERY_DEV_CAP()
889 field &= 0xf; in mlx4_QUERY_DEV_CAP()
890 if (field) { in mlx4_QUERY_DEV_CAP()
892 dev_cap->max_rss_tbl_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
895 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); in mlx4_QUERY_DEV_CAP()
896 dev_cap->max_rdma_global = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
897 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); in mlx4_QUERY_DEV_CAP()
898 dev_cap->local_ca_ack_delay = field & 0x1f; in mlx4_QUERY_DEV_CAP()
899 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP()
900 dev_cap->num_ports = field & 0xf; in mlx4_QUERY_DEV_CAP()
901 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
902 dev_cap->max_msg_sz = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
903 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); in mlx4_QUERY_DEV_CAP()
904 if (field & 0x10) in mlx4_QUERY_DEV_CAP()
906 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); in mlx4_QUERY_DEV_CAP()
907 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
909 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; in mlx4_QUERY_DEV_CAP()
910 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
912 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP()
913 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
915 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP()
916 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
918 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
919 dev_cap->fs_max_num_qp_per_entry = field; in mlx4_QUERY_DEV_CAP()
920 MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET); in mlx4_QUERY_DEV_CAP()
921 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
923 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP()
924 if (field & 0x1) in mlx4_QUERY_DEV_CAP()
928 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP()
929 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
934 MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET); in mlx4_QUERY_DEV_CAP()
935 dev_cap->wol_port[1] = !!(field & 0x20); in mlx4_QUERY_DEV_CAP()
936 dev_cap->wol_port[2] = !!(field & 0x40); in mlx4_QUERY_DEV_CAP()
937 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); in mlx4_QUERY_DEV_CAP()
938 dev_cap->reserved_uars = field >> 4; in mlx4_QUERY_DEV_CAP()
939 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
940 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); in mlx4_QUERY_DEV_CAP()
941 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
942 dev_cap->min_page_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
944 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP()
945 if (field & 0x80) { in mlx4_QUERY_DEV_CAP()
946 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
947 dev_cap->bf_reg_size = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
948 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); in mlx4_QUERY_DEV_CAP()
949 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) in mlx4_QUERY_DEV_CAP()
950 field = 3; in mlx4_QUERY_DEV_CAP()
951 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
956 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); in mlx4_QUERY_DEV_CAP()
957 dev_cap->max_sq_sg = field; in mlx4_QUERY_DEV_CAP()
961 MLX4_GET(field, outbox, QUERY_DEV_CAP_USER_MAC_EN_OFFSET); in mlx4_QUERY_DEV_CAP()
962 if (field & (1 << 2)) in mlx4_QUERY_DEV_CAP()
964 MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
965 if (field & 0x1) in mlx4_QUERY_DEV_CAP()
967 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
968 dev_cap->max_qp_per_mcg = 1 << field; in mlx4_QUERY_DEV_CAP()
969 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
970 dev_cap->reserved_mgms = field & 0xf; in mlx4_QUERY_DEV_CAP()
971 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
972 dev_cap->max_mcgs = 1 << field; in mlx4_QUERY_DEV_CAP()
973 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); in mlx4_QUERY_DEV_CAP()
974 dev_cap->reserved_pds = field >> 4; in mlx4_QUERY_DEV_CAP()
975 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); in mlx4_QUERY_DEV_CAP()
976 dev_cap->max_pds = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
977 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); in mlx4_QUERY_DEV_CAP()
978 dev_cap->reserved_xrcds = field >> 4; in mlx4_QUERY_DEV_CAP()
979 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); in mlx4_QUERY_DEV_CAP()
980 dev_cap->max_xrcds = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
1003 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
1004 dev_cap->max_srq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
1005 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
1006 dev_cap->max_qp_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
1007 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
1008 dev_cap->resize_srq = field & 1; in mlx4_QUERY_DEV_CAP()
1009 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); in mlx4_QUERY_DEV_CAP()
1010 dev_cap->max_rq_sg = field; in mlx4_QUERY_DEV_CAP()
1013 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP()
1014 if (field & (1 << 4)) in mlx4_QUERY_DEV_CAP()
1016 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
1018 if (field & (1 << 6)) in mlx4_QUERY_DEV_CAP()
1020 if (field & (1 << 7)) in mlx4_QUERY_DEV_CAP()
1028 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP()
1029 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
1031 if (field & (1 << 2)) in mlx4_QUERY_DEV_CAP()
1033 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); in mlx4_QUERY_DEV_CAP()
1034 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
1036 if (field & 0x40) in mlx4_QUERY_DEV_CAP()
1051 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); in mlx4_QUERY_DEV_CAP()
1052 if (field & 1<<6) in mlx4_QUERY_DEV_CAP()
1054 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP()
1055 if (field & 1<<3) in mlx4_QUERY_DEV_CAP()
1057 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
1190 u8 field; in mlx4_QUERY_PORT() local
1207 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_PORT()
1208 port_cap->max_vl = field >> 4; in mlx4_QUERY_PORT()
1209 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); in mlx4_QUERY_PORT()
1210 port_cap->ib_mtu = field >> 4; in mlx4_QUERY_PORT()
1211 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1212 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); in mlx4_QUERY_PORT()
1213 port_cap->max_gids = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1214 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); in mlx4_QUERY_PORT()
1215 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1234 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); in mlx4_QUERY_PORT()
1235 port_cap->link_state = (field & 0x80) >> 7; in mlx4_QUERY_PORT()
1236 port_cap->supported_port_types = field & 3; in mlx4_QUERY_PORT()
1237 port_cap->suggested_type = (field >> 3) & 1; in mlx4_QUERY_PORT()
1238 port_cap->default_sense = (field >> 4) & 1; in mlx4_QUERY_PORT()
1239 port_cap->dmfs_optimized_state = (field >> 5) & 1; in mlx4_QUERY_PORT()
1240 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); in mlx4_QUERY_PORT()
1241 port_cap->ib_mtu = field & 0xf; in mlx4_QUERY_PORT()
1242 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); in mlx4_QUERY_PORT()
1243 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1244 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); in mlx4_QUERY_PORT()
1245 port_cap->max_gids = 1 << (field >> 4); in mlx4_QUERY_PORT()
1246 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1247 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); in mlx4_QUERY_PORT()
1248 port_cap->max_vl = field & 0xf; in mlx4_QUERY_PORT()
1249 port_cap->max_tc_eth = field >> 4; in mlx4_QUERY_PORT()
1250 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); in mlx4_QUERY_PORT()
1251 port_cap->log_max_macs = field & 0xf; in mlx4_QUERY_PORT()
1252 port_cap->log_max_vlans = field >> 4; in mlx4_QUERY_PORT()
1280 u8 field; in mlx4_QUERY_DEV_CAP_wrapper() local
1318 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1319 field &= ~0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1320 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1321 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1324 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1325 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1326 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1329 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP_wrapper()
1330 field &= 0xd7; in mlx4_QUERY_DEV_CAP_wrapper()
1331 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP_wrapper()
1334 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1335 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1336 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1339 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1340 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1341 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1351 MLX4_GET(field, outbox->buf, in mlx4_QUERY_DEV_CAP_wrapper()
1353 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1354 MLX4_PUT(outbox->buf, field, in mlx4_QUERY_DEV_CAP_wrapper()
1359 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1360 field &= ~0x80; in mlx4_QUERY_DEV_CAP_wrapper()
1361 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1370 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1371 field &= 0xfe; in mlx4_QUERY_DEV_CAP_wrapper()
1372 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1379 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP_wrapper()
1380 field &= 0xef; in mlx4_QUERY_DEV_CAP_wrapper()
1381 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP_wrapper()
1384 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1385 field &= 0xfb; in mlx4_QUERY_DEV_CAP_wrapper()
1386 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1492 u16 field; in mlx4_get_slave_pkey_gid_tbl_len() local
1507 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); in mlx4_get_slave_pkey_gid_tbl_len()
1508 *gid_tbl_len = field; in mlx4_get_slave_pkey_gid_tbl_len()
1510 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); in mlx4_get_slave_pkey_gid_tbl_len()
1511 *pkey_tbl_len = field; in mlx4_get_slave_pkey_gid_tbl_len()
2302 u16 field; in mlx4_INIT_PORT() local
2329 field = 128 << dev->caps.ib_mtu_cap[port]; in mlx4_INIT_PORT()
2330 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); in mlx4_INIT_PORT()
2331 field = dev->caps.gid_table_len[port]; in mlx4_INIT_PORT()
2332 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); in mlx4_INIT_PORT()
2333 field = dev->caps.pkey_table_len[port]; in mlx4_INIT_PORT()
2334 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); in mlx4_INIT_PORT()