Lines Matching +full:- +full:eq
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) in get_async_ev_mask()
91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) in get_async_ev_mask()
97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) in eq_set_ci() argument
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | in eq_set_ci()
101 eq->doorbell); in eq_set_ci()
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, in get_eqe() argument
109 /* (entry & (eq->nent - 1)) gives us a cyclic array */ in get_eqe()
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; in get_eqe()
118 …return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % … in get_eqe()
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) in next_eqe_sw() argument
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); in next_eqe_sw()
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; in next_slave_event_eqe()
131 return (!!(eqe->owner & 0x80) ^ in next_slave_event_eqe()
132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? in next_slave_event_eqe()
144 struct mlx4_dev *dev = &priv->dev; in mlx4_gen_slave_eqe()
145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; in mlx4_gen_slave_eqe()
152 slave = eqe->slave_id; in mlx4_gen_slave_eqe()
154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE && in mlx4_gen_slave_eqe()
155 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN && in mlx4_gen_slave_eqe()
167 for (i = 0; i <= dev->persist->num_vfs; i++) { in mlx4_gen_slave_eqe()
169 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT && in mlx4_gen_slave_eqe()
170 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) { in mlx4_gen_slave_eqe()
171 phys_port = eqe->event.port_mgmt_change.port; in mlx4_gen_slave_eqe()
175 eqe->event.port_mgmt_change.port = slave_port; in mlx4_gen_slave_eqe()
181 eqe->event.port_mgmt_change.port = phys_port; in mlx4_gen_slave_eqe()
189 ++slave_eq->cons; in mlx4_gen_slave_eqe()
197 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; in slave_event()
201 spin_lock_irqsave(&slave_eq->event_lock, flags); in slave_event()
202 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; in slave_event()
203 if ((!!(s_eqe->owner & 0x80)) ^ in slave_event()
204 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { in slave_event()
207 spin_unlock_irqrestore(&slave_eq->event_lock, flags); in slave_event()
211 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1); in slave_event()
212 s_eqe->slave_id = slave; in slave_event()
215 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; in slave_event()
216 ++slave_eq->prod; in slave_event()
218 queue_work(priv->mfunc.master.comm_wq, in slave_event()
219 &priv->mfunc.master.slave_event_work); in slave_event()
220 spin_unlock_irqrestore(&slave_eq->event_lock, flags); in slave_event()
228 if (slave < 0 || slave > dev->persist->num_vfs || in mlx4_slave_event()
229 slave == dev->caps.function || in mlx4_slave_event()
230 !priv->mfunc.master.slave_state[slave].active) in mlx4_slave_event()
240 struct mlx4_dev *dev = &priv->dev; in mlx4_set_eq_affinity_hint()
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; in mlx4_set_eq_affinity_hint() local
243 if (!cpumask_available(eq->affinity_mask) || in mlx4_set_eq_affinity_hint()
244 cpumask_empty(eq->affinity_mask)) in mlx4_set_eq_affinity_hint()
247 hint_err = irq_update_affinity_hint(eq->irq, eq->affinity_mask); in mlx4_set_eq_affinity_hint()
258 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; in mlx4_gen_pkey_eqe()
260 if (!s_slave->active) in mlx4_gen_pkey_eqe()
278 if (dev->persist->num_vfs < slave) in mlx4_gen_guid_change_eqe()
297 if (dev->persist->num_vfs < slave) in mlx4_gen_port_state_change_eqe()
314 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; in mlx4_get_slave_port_state()
317 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_get_slave_port_state()
318 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { in mlx4_get_slave_port_state()
331 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; in mlx4_set_slave_port_state()
334 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_set_slave_port_state()
335 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { in mlx4_set_slave_port_state()
338 return -1; in mlx4_set_slave_port_state()
352 for (i = 0; i < dev->persist->num_vfs + 1; i++) in set_all_slave_state()
373 int ret = -1; in set_and_calc_slave_port_state()
380 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in set_and_calc_slave_port_state()
381 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { in set_and_calc_slave_port_state()
387 ctx = &priv->mfunc.master.slave_state[slave]; in set_and_calc_slave_port_state()
388 spin_lock_irqsave(&ctx->lock, flags); in set_and_calc_slave_port_state()
426 spin_unlock_irqrestore(&ctx->lock, flags); in set_and_calc_slave_port_state()
458 struct mlx4_dev *dev = &priv->dev; in mlx4_master_handle_slave_flr()
459 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; in mlx4_master_handle_slave_flr()
466 for (i = 0 ; i < dev->num_slaves; i++) { in mlx4_master_handle_slave_flr()
476 if (dev->persist->interface_state & in mlx4_master_handle_slave_flr()
480 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_handle_slave_flr()
483 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_handle_slave_flr()
494 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) in mlx4_eq_int() argument
510 int eqe_size = dev->caps.eqe_size; in mlx4_eq_int()
512 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { in mlx4_eq_int()
514 * Make sure we read EQ entry contents after we've in mlx4_eq_int()
519 switch (eqe->type) { in mlx4_eq_int()
521 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; in mlx4_eq_int()
533 mlx4_dbg(dev, "event %d arrived\n", eqe->type); in mlx4_eq_int()
538 be32_to_cpu(eqe->event.qp.qpn) in mlx4_eq_int()
540 if (ret && ret != -ENOENT) { in mlx4_eq_int()
541 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", in mlx4_eq_int()
542 eqe->type, eqe->subtype, in mlx4_eq_int()
543 eq->eqn, eq->cons_index, ret); in mlx4_eq_int()
547 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
553 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & in mlx4_eq_int()
554 0xffffff, eqe->type); in mlx4_eq_int()
558 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n", in mlx4_eq_int()
559 __func__, be32_to_cpu(eqe->event.srq.srqn), in mlx4_eq_int()
560 eq->eqn); in mlx4_eq_int()
567 be32_to_cpu(eqe->event.srq.srqn) in mlx4_eq_int()
570 if (ret && ret != -ENOENT) { in mlx4_eq_int()
571 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", in mlx4_eq_int()
572 eqe->type, eqe->subtype, in mlx4_eq_int()
573 eq->eqn, eq->cons_index, ret); in mlx4_eq_int()
576 if (eqe->type == in mlx4_eq_int()
580 be32_to_cpu(eqe->event.srq.srqn), in mlx4_eq_int()
581 eqe->type, eqe->subtype); in mlx4_eq_int()
583 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
584 if (eqe->type == in mlx4_eq_int()
587 __func__, eqe->type, in mlx4_eq_int()
588 eqe->subtype, slave); in mlx4_eq_int()
593 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & in mlx4_eq_int()
594 0xffffff, eqe->type); in mlx4_eq_int()
599 be16_to_cpu(eqe->event.cmd.token), in mlx4_eq_int()
600 eqe->event.cmd.status, in mlx4_eq_int()
601 be64_to_cpu(eqe->event.cmd.out_param)); in mlx4_eq_int()
606 port = be32_to_cpu(eqe->event.port_change.port) >> 28; in mlx4_eq_int()
608 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { in mlx4_eq_int()
611 mlx4_priv(dev)->sense.do_sense_port[port] = 1; in mlx4_eq_int()
614 for (i = 0; i < dev->persist->num_vfs + 1; in mlx4_eq_int()
620 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { in mlx4_eq_int()
625 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state; in mlx4_eq_int()
626 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { in mlx4_eq_int()
627 eqe->event.port_change.port = in mlx4_eq_int()
629 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) in mlx4_eq_int()
641 eqe->event.port_change.port = in mlx4_eq_int()
643 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) in mlx4_eq_int()
653 mlx4_priv(dev)->sense.do_sense_port[port] = 0; in mlx4_eq_int()
657 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) in mlx4_eq_int()
659 i < dev->persist->num_vfs + 1; in mlx4_eq_int()
667 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state; in mlx4_eq_int()
668 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { in mlx4_eq_int()
669 eqe->event.port_change.port = in mlx4_eq_int()
671 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) in mlx4_eq_int()
677 /* port-up event will be sent to a slave when the in mlx4_eq_int()
678 * slave's alias-guid is set. This is done in alias_GUID.c in mlx4_eq_int()
687 eqe->event.cq_err.syndrome == 1 ? in mlx4_eq_int()
689 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); in mlx4_eq_int()
693 be32_to_cpu(eqe->event.cq_err.cqn) in mlx4_eq_int()
695 if (ret && ret != -ENOENT) { in mlx4_eq_int()
696 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", in mlx4_eq_int()
697 eqe->type, eqe->subtype, in mlx4_eq_int()
698 eq->eqn, eq->cons_index, ret); in mlx4_eq_int()
702 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
708 be32_to_cpu(eqe->event.cq_err.cqn) in mlx4_eq_int()
710 eqe->type); in mlx4_eq_int()
714 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); in mlx4_eq_int()
718 atomic_inc(&priv->opreq_count); in mlx4_eq_int()
722 queue_work(mlx4_wq, &priv->opreq_task); in mlx4_eq_int()
730 memcpy(&priv->mfunc.master.comm_arm_bit_vector, in mlx4_eq_int()
731 eqe->event.comm_channel_arm.bit_vec, in mlx4_eq_int()
732 sizeof(eqe->event.comm_channel_arm.bit_vec)); in mlx4_eq_int()
733 queue_work(priv->mfunc.master.comm_wq, in mlx4_eq_int()
734 &priv->mfunc.master.comm_work); in mlx4_eq_int()
738 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); in mlx4_eq_int()
740 mlx4_warn(dev, "Non-master function received FLR event\n"); in mlx4_eq_int()
746 if (flr_slave >= dev->num_slaves) { in mlx4_eq_int()
754 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_eq_int()
756 priv->mfunc.master.slave_state[flr_slave].active = false; in mlx4_eq_int()
757 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; in mlx4_eq_int()
758 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; in mlx4_eq_int()
760 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_eq_int()
763 queue_work(priv->mfunc.master.comm_wq, in mlx4_eq_int()
764 &priv->mfunc.master.slave_flr_event_work); in mlx4_eq_int()
768 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { in mlx4_eq_int()
770 for (i = 0; i < dev->num_slaves; i++) { in mlx4_eq_int()
773 if (i == dev->caps.function) in mlx4_eq_int()
778 be16_to_cpu(eqe->event.warming.warning_threshold), in mlx4_eq_int()
779 be16_to_cpu(eqe->event.warming.current_temperature)); in mlx4_eq_int()
781 …mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x,… in mlx4_eq_int()
782 eqe->type, eqe->subtype, eq->eqn, in mlx4_eq_int()
783 eq->cons_index, eqe->owner, eq->nent, in mlx4_eq_int()
784 eqe->slave_id, in mlx4_eq_int()
785 !!(eqe->owner & 0x80) ^ in mlx4_eq_int()
786 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); in mlx4_eq_int()
796 switch (eqe->subtype) { in mlx4_eq_int()
799 eqe->event.bad_cable.port); in mlx4_eq_int()
806 …"Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x,… in mlx4_eq_int()
807 eqe->type, eqe->subtype, eq->eqn, in mlx4_eq_int()
808 eq->cons_index, eqe->owner, eq->nent, in mlx4_eq_int()
809 !!(eqe->owner & 0x80) ^ in mlx4_eq_int()
810 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); in mlx4_eq_int()
818 …mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ow… in mlx4_eq_int()
819 eqe->type, eqe->subtype, eq->eqn, in mlx4_eq_int()
820 eq->cons_index, eqe->owner, eq->nent, in mlx4_eq_int()
821 eqe->slave_id, in mlx4_eq_int()
822 !!(eqe->owner & 0x80) ^ in mlx4_eq_int()
823 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); in mlx4_eq_int()
827 ++eq->cons_index; in mlx4_eq_int()
839 eq_set_ci(eq, 0); in mlx4_eq_int()
844 eq_set_ci(eq, 1); in mlx4_eq_int()
856 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); in mlx4_interrupt()
858 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) in mlx4_interrupt()
859 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); in mlx4_interrupt()
866 struct mlx4_eq *eq = eq_ptr; in mlx4_msi_x_interrupt() local
867 struct mlx4_dev *dev = eq->dev; in mlx4_msi_x_interrupt()
869 mlx4_eq_int(dev, eq); in mlx4_msi_x_interrupt()
871 /* MSI-X vectors always belong to us */ in mlx4_msi_x_interrupt()
883 priv->mfunc.master.slave_state[slave].event_eq; in mlx4_MAP_EQ_wrapper()
884 u32 in_modifier = vhcr->in_modifier; in mlx4_MAP_EQ_wrapper()
886 u64 in_param = vhcr->in_param; in mlx4_MAP_EQ_wrapper()
890 if (slave == dev->caps.function) in mlx4_MAP_EQ_wrapper()
897 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; in mlx4_MAP_EQ_wrapper()
913 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, in mlx4_SW2HW_EQ()
927 * Each UAR holds 4 EQ doorbells. To figure out how many UARs in mlx4_num_eq_uar()
931 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 - in mlx4_num_eq_uar()
932 dev->caps.reserved_eqs / 4 + 1; in mlx4_num_eq_uar()
935 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) in mlx4_get_eq_uar() argument
940 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; in mlx4_get_eq_uar()
942 if (!priv->eq_table.uar_map[index]) { in mlx4_get_eq_uar()
943 priv->eq_table.uar_map[index] = in mlx4_get_eq_uar()
945 pci_resource_start(dev->persist->pdev, 2) + in mlx4_get_eq_uar()
946 ((eq->eqn / 4) << (dev->uar_page_shift)), in mlx4_get_eq_uar()
947 (1 << (dev->uar_page_shift))); in mlx4_get_eq_uar()
948 if (!priv->eq_table.uar_map[index]) { in mlx4_get_eq_uar()
949 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", in mlx4_get_eq_uar()
950 eq->eqn); in mlx4_get_eq_uar()
955 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); in mlx4_get_eq_uar()
964 if (priv->eq_table.uar_map[i]) { in mlx4_unmap_uar()
965 iounmap(priv->eq_table.uar_map[i]); in mlx4_unmap_uar()
966 priv->eq_table.uar_map[i] = NULL; in mlx4_unmap_uar()
971 u8 intr, struct mlx4_eq *eq) in mlx4_create_eq() argument
980 int err = -ENOMEM; in mlx4_create_eq()
983 eq->dev = dev; in mlx4_create_eq()
984 eq->nent = roundup_pow_of_two(max(nent, 2)); in mlx4_create_eq()
988 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; in mlx4_create_eq()
990 eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list), in mlx4_create_eq()
992 if (!eq->page_list) in mlx4_create_eq()
996 eq->page_list[i].buf = NULL; in mlx4_create_eq()
1005 eq_context = mailbox->buf; in mlx4_create_eq()
1008 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist-> in mlx4_create_eq()
1009 pdev->dev, in mlx4_create_eq()
1012 if (!eq->page_list[i].buf) in mlx4_create_eq()
1016 eq->page_list[i].map = t; in mlx4_create_eq()
1019 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); in mlx4_create_eq()
1020 if (eq->eqn == -1) in mlx4_create_eq()
1023 eq->doorbell = mlx4_get_eq_uar(dev, eq); in mlx4_create_eq()
1024 if (!eq->doorbell) { in mlx4_create_eq()
1025 err = -ENOMEM; in mlx4_create_eq()
1029 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); in mlx4_create_eq()
1033 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); in mlx4_create_eq()
1037 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | in mlx4_create_eq()
1039 eq_context->log_eq_size = ilog2(eq->nent); in mlx4_create_eq()
1040 eq_context->intr = intr; in mlx4_create_eq()
1041 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; in mlx4_create_eq()
1043 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); in mlx4_create_eq()
1044 eq_context->mtt_base_addr_h = mtt_addr >> 32; in mlx4_create_eq()
1045 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); in mlx4_create_eq()
1047 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); in mlx4_create_eq()
1056 eq->cons_index = 0; in mlx4_create_eq()
1058 INIT_LIST_HEAD(&eq->tasklet_ctx.list); in mlx4_create_eq()
1059 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list); in mlx4_create_eq()
1060 spin_lock_init(&eq->tasklet_ctx.lock); in mlx4_create_eq()
1061 tasklet_setup(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb); in mlx4_create_eq()
1066 mlx4_mtt_cleanup(dev, &eq->mtt); in mlx4_create_eq()
1069 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); in mlx4_create_eq()
1073 if (eq->page_list[i].buf) in mlx4_create_eq()
1074 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, in mlx4_create_eq()
1075 eq->page_list[i].buf, in mlx4_create_eq()
1076 eq->page_list[i].map); in mlx4_create_eq()
1081 kfree(eq->page_list); in mlx4_create_eq()
1089 struct mlx4_eq *eq) in mlx4_free_eq() argument
1097 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; in mlx4_free_eq()
1099 err = mlx4_HW2SW_EQ(dev, eq->eqn); in mlx4_free_eq()
1103 synchronize_irq(eq->irq); in mlx4_free_eq()
1104 tasklet_disable(&eq->tasklet_ctx.task); in mlx4_free_eq()
1106 mlx4_mtt_cleanup(dev, &eq->mtt); in mlx4_free_eq()
1108 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, in mlx4_free_eq()
1109 eq->page_list[i].buf, in mlx4_free_eq()
1110 eq->page_list[i].map); in mlx4_free_eq()
1112 kfree(eq->page_list); in mlx4_free_eq()
1113 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); in mlx4_free_eq()
1118 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; in mlx4_free_irqs()
1121 if (eq_table->have_irq) in mlx4_free_irqs()
1122 free_irq(dev->persist->pdev->irq, dev); in mlx4_free_irqs()
1124 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) in mlx4_free_irqs()
1125 if (eq_table->eq[i].have_irq) { in mlx4_free_irqs()
1126 free_cpumask_var(eq_table->eq[i].affinity_mask); in mlx4_free_irqs()
1127 irq_update_affinity_hint(eq_table->eq[i].irq, NULL); in mlx4_free_irqs()
1128 free_irq(eq_table->eq[i].irq, eq_table->eq + i); in mlx4_free_irqs()
1129 eq_table->eq[i].have_irq = 0; in mlx4_free_irqs()
1132 kfree(eq_table->irq_names); in mlx4_free_irqs()
1139 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev, in mlx4_map_clr_int()
1140 priv->fw.clr_int_bar) + in mlx4_map_clr_int()
1141 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); in mlx4_map_clr_int()
1142 if (!priv->clr_base) { in mlx4_map_clr_int()
1144 return -ENOMEM; in mlx4_map_clr_int()
1154 iounmap(priv->clr_base); in mlx4_unmap_clr_int()
1161 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, in mlx4_alloc_eq_table()
1162 sizeof(*priv->eq_table.eq), GFP_KERNEL); in mlx4_alloc_eq_table()
1163 if (!priv->eq_table.eq) in mlx4_alloc_eq_table()
1164 return -ENOMEM; in mlx4_alloc_eq_table()
1171 kfree(mlx4_priv(dev)->eq_table.eq); in mlx4_free_eq_table()
1180 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), in mlx4_init_eq_table()
1181 sizeof(*priv->eq_table.uar_map), in mlx4_init_eq_table()
1183 if (!priv->eq_table.uar_map) { in mlx4_init_eq_table()
1184 err = -ENOMEM; in mlx4_init_eq_table()
1188 err = mlx4_bitmap_init(&priv->eq_table.bitmap, in mlx4_init_eq_table()
1189 roundup_pow_of_two(dev->caps.num_eqs), in mlx4_init_eq_table()
1190 dev->caps.num_eqs - 1, in mlx4_init_eq_table()
1191 dev->caps.reserved_eqs, in mlx4_init_eq_table()
1192 roundup_pow_of_two(dev->caps.num_eqs) - in mlx4_init_eq_table()
1193 dev->caps.num_eqs); in mlx4_init_eq_table()
1198 priv->eq_table.uar_map[i] = NULL; in mlx4_init_eq_table()
1205 priv->eq_table.clr_mask = in mlx4_init_eq_table()
1206 swab32(1 << (priv->eq_table.inta_pin & 31)); in mlx4_init_eq_table()
1207 priv->eq_table.clr_int = priv->clr_base + in mlx4_init_eq_table()
1208 (priv->eq_table.inta_pin < 32 ? 4 : 0); in mlx4_init_eq_table()
1211 priv->eq_table.irq_names = in mlx4_init_eq_table()
1213 (dev->caps.num_comp_vectors + 1), in mlx4_init_eq_table()
1215 if (!priv->eq_table.irq_names) { in mlx4_init_eq_table()
1216 err = -ENOMEM; in mlx4_init_eq_table()
1220 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { in mlx4_init_eq_table()
1224 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]); in mlx4_init_eq_table()
1226 struct mlx4_eq *eq = &priv->eq_table.eq[i]; in mlx4_init_eq_table() local
1228 int port = find_first_bit(eq->actv_ports.ports, in mlx4_init_eq_table()
1229 dev->caps.num_ports) + 1; in mlx4_init_eq_table()
1231 if (port <= dev->caps.num_ports) { in mlx4_init_eq_table()
1233 &mlx4_priv(dev)->port[port]; in mlx4_init_eq_table()
1235 if (!info->rmap) { in mlx4_init_eq_table()
1236 info->rmap = alloc_irq_cpu_rmap( in mlx4_init_eq_table()
1238 if (!info->rmap) { in mlx4_init_eq_table()
1240 err = -ENOMEM; in mlx4_init_eq_table()
1246 info->rmap, eq->irq); in mlx4_init_eq_table()
1251 err = mlx4_create_eq(dev, dev->quotas.cq + in mlx4_init_eq_table()
1253 (dev->flags & MLX4_FLAG_MSI_X) ? in mlx4_init_eq_table()
1254 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0, in mlx4_init_eq_table()
1255 eq); in mlx4_init_eq_table()
1261 if (dev->flags & MLX4_FLAG_MSI_X) { in mlx4_init_eq_table()
1264 snprintf(priv->eq_table.irq_names + in mlx4_init_eq_table()
1267 "mlx4-async@pci:%s", in mlx4_init_eq_table()
1268 pci_name(dev->persist->pdev)); in mlx4_init_eq_table()
1269 eq_name = priv->eq_table.irq_names + in mlx4_init_eq_table()
1272 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, in mlx4_init_eq_table()
1274 priv->eq_table.eq + MLX4_EQ_ASYNC); in mlx4_init_eq_table()
1278 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; in mlx4_init_eq_table()
1280 snprintf(priv->eq_table.irq_names, in mlx4_init_eq_table()
1283 pci_name(dev->persist->pdev)); in mlx4_init_eq_table()
1284 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, in mlx4_init_eq_table()
1285 IRQF_SHARED, priv->eq_table.irq_names, dev); in mlx4_init_eq_table()
1289 priv->eq_table.have_irq = 1; in mlx4_init_eq_table()
1293 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); in mlx4_init_eq_table()
1295 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", in mlx4_init_eq_table()
1296 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err); in mlx4_init_eq_table()
1298 /* arm ASYNC eq */ in mlx4_init_eq_table()
1299 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1); in mlx4_init_eq_table()
1305 mlx4_free_eq(dev, &priv->eq_table.eq[--i]); in mlx4_init_eq_table()
1307 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_init_eq_table()
1308 if (mlx4_priv(dev)->port[i].rmap) { in mlx4_init_eq_table()
1309 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); in mlx4_init_eq_table()
1310 mlx4_priv(dev)->port[i].rmap = NULL; in mlx4_init_eq_table()
1322 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); in mlx4_init_eq_table()
1325 kfree(priv->eq_table.uar_map); in mlx4_init_eq_table()
1336 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); in mlx4_cleanup_eq_table()
1339 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_cleanup_eq_table()
1340 if (mlx4_priv(dev)->port[i].rmap) { in mlx4_cleanup_eq_table()
1341 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); in mlx4_cleanup_eq_table()
1342 mlx4_priv(dev)->port[i].rmap = NULL; in mlx4_cleanup_eq_table()
1348 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) in mlx4_cleanup_eq_table()
1349 mlx4_free_eq(dev, &priv->eq_table.eq[i]); in mlx4_cleanup_eq_table()
1355 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); in mlx4_cleanup_eq_table()
1357 kfree(priv->eq_table.uar_map); in mlx4_cleanup_eq_table()
1381 /* Map the new eq to handle all asynchronous events */ in mlx4_test_interrupt()
1383 priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn); in mlx4_test_interrupt()
1385 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); in mlx4_test_interrupt()
1397 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); in mlx4_test_interrupt()
1409 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) || in mlx4_is_eq_vector_valid()
1413 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports); in mlx4_is_eq_vector_valid()
1423 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) in mlx4_get_eqs_per_port()
1424 sum += !!test_bit(port - 1, in mlx4_get_eqs_per_port()
1425 priv->eq_table.eq[i].actv_ports.ports); in mlx4_get_eqs_per_port()
1436 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1)) in mlx4_is_eq_shared()
1437 return -EINVAL; in mlx4_is_eq_shared()
1439 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports, in mlx4_is_eq_shared()
1440 dev->caps.num_ports) > 1); in mlx4_is_eq_shared()
1446 return mlx4_priv(dev)->port[port].rmap; in mlx4_get_cpu_rmap()
1454 u32 min_ref_count_val = (u32)-1; in mlx4_assign_eq()
1459 mutex_lock(&priv->msix_ctl.pool_lock); in mlx4_assign_eq()
1460 if (requested_vector < (dev->caps.num_comp_vectors + 1) && in mlx4_assign_eq()
1463 if (test_bit(port - 1, in mlx4_assign_eq()
1464 priv->eq_table.eq[requested_vector].actv_ports.ports)) { in mlx4_assign_eq()
1467 struct mlx4_eq *eq; in mlx4_assign_eq() local
1473 eq = &priv->eq_table.eq[requested_vector]; in mlx4_assign_eq()
1474 if (requested_vector < dev->caps.num_comp_vectors + 1 && in mlx4_assign_eq()
1475 test_bit(port - 1, eq->actv_ports.ports)) { in mlx4_assign_eq()
1482 requested_vector = -1; in mlx4_assign_eq()
1483 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1; in mlx4_assign_eq()
1485 struct mlx4_eq *eq = &priv->eq_table.eq[i]; in mlx4_assign_eq() local
1487 if (min_ref_count_val > eq->ref_count && in mlx4_assign_eq()
1488 test_bit(port - 1, eq->actv_ports.ports)) { in mlx4_assign_eq()
1489 min_ref_count_val = eq->ref_count; in mlx4_assign_eq()
1495 err = -ENOSPC; in mlx4_assign_eq()
1502 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) && in mlx4_assign_eq()
1503 dev->flags & MLX4_FLAG_MSI_X) { in mlx4_assign_eq()
1504 set_bit(*prequested_vector, priv->msix_ctl.pool_bm); in mlx4_assign_eq()
1505 snprintf(priv->eq_table.irq_names + in mlx4_assign_eq()
1507 MLX4_IRQNAME_SIZE, "mlx4-%d@%s", in mlx4_assign_eq()
1508 *prequested_vector, dev_name(&dev->persist->pdev->dev)); in mlx4_assign_eq()
1510 err = request_irq(priv->eq_table.eq[*prequested_vector].irq, in mlx4_assign_eq()
1512 &priv->eq_table.irq_names[*prequested_vector << 5], in mlx4_assign_eq()
1513 priv->eq_table.eq + *prequested_vector); in mlx4_assign_eq()
1516 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); in mlx4_assign_eq()
1517 *prequested_vector = -1; in mlx4_assign_eq()
1522 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); in mlx4_assign_eq()
1523 priv->eq_table.eq[*prequested_vector].have_irq = 1; in mlx4_assign_eq()
1528 priv->eq_table.eq[*prequested_vector].ref_count++; in mlx4_assign_eq()
1531 mutex_unlock(&priv->msix_ctl.pool_lock); in mlx4_assign_eq()
1546 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq; in mlx4_eq_get_irq()
1555 mutex_lock(&priv->msix_ctl.pool_lock); in mlx4_release_eq()
1556 priv->eq_table.eq[eq_vec].ref_count--; in mlx4_release_eq()
1558 /* once we allocated EQ, we don't release it because it might be binded in mlx4_release_eq()
1561 mutex_unlock(&priv->msix_ctl.pool_lock); in mlx4_release_eq()