103 	return wed_r32(dev, MTK_WED_RESET);  in mtk_wed_read_reset()
171 	return wed_r32(dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_WO_STATUS);  in mtk_wed_wo_read_status()
513 	wed_r32(dev, MTK_WED_EXT_INT_MASK);  in mtk_wed_set_ext_int()
543 		cur_idx = wed_r32(dev,  in mtk_wed_check_wfdma_rx_fill()
706 		wed_r32(dev, MTK_WED_PCIE_INT_CTRL);  in mtk_wed_bus_init()
713 		wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);  in mtk_wed_bus_init()
904 		if (!(wed_r32(dev, MTK_WED_RESET) & MTK_WED_RESET_RX_ROUTE_QM))  in mtk_wed_route_qm_hw_init()
1013 	return !!(wed_r32(dev, reg) & mask);  in mtk_wed_check_busy()
1189 		val = wed_r32(dev, MTK_WED_TX_BM_INTF);  in mtk_wed_reset_dma()
1482 		wed_r32(dev, MTK_WED_EXT_INT_MASK1);  in mtk_wed_start()
1483 		wed_r32(dev, MTK_WED_EXT_INT_MASK2);  in mtk_wed_start()
1557 		dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);  in mtk_wed_attach()
1687 	val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);  in mtk_wed_irq_get()
1695 	val = wed_r32(dev, MTK_WED_INT_STATUS);  in mtk_wed_irq_get()
1868 		.reg_read = wed_r32,  in mtk_wed_add_hw()