208 	u32 offset;
282 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)  in mtk_w32()
287 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)  in mtk_r32()
292 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)  in mtk_m32()
294 	u32 val;  in mtk_m32()
319 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,  in _mtk_mdio_write_c22()
320 			       u32 write_data)  in _mtk_mdio_write_c22()
343 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,  in _mtk_mdio_write_c45()
344 			       u32 devad, u32 phy_reg, u32 write_data)  in _mtk_mdio_write_c45()
379 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)  in _mtk_mdio_read_c22()
401 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,  in _mtk_mdio_read_c45()
402 			      u32 devad, u32 phy_reg)  in _mtk_mdio_read_c45()
470 	u32 val;  in mt7621_gmac0_rgmii_adjust()
536 	u32 i;  in mtk_mac_config()
630 				   ~(u32)SYSCFG0_SGMII_MASK);  in mtk_mac_config()
667 	u32 mcr_cur, mcr_new;  in mtk_mac_finish()
693 	u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));  in mtk_mac_link_down()
703 	u32 ofs, val;  in mtk_set_queue_speed()
775 	u32 mcr;  in mtk_mac_link_up()
821 	u32 val;  in mtk_mdio_init()
887 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)  in mtk_tx_irq_disable()
890 	u32 val;  in mtk_tx_irq_disable()
898 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)  in mtk_tx_irq_enable()
901 	u32 val;  in mtk_tx_irq_enable()
909 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)  in mtk_rx_irq_disable()
912 	u32 val;  in mtk_rx_irq_disable()
920 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)  in mtk_rx_irq_enable()
923 	u32 val;  in mtk_rx_irq_enable()
1186 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)  in mtk_qdma_phys_to_virt()
1192 					     void *txd, u32 txd_size)  in mtk_desc_to_tx_buf()
1205 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)  in txd_to_idx()
1293 	u32 data;  in mtk_tx_set_dma_desc_v1()
1323 	u32 data;  in mtk_tx_set_dma_desc_v2()
1908 			struct xdp_frame **frames, u32 flags)  in mtk_xdp_xmit()
1932 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,  in mtk_xdp_run()
1939 	u32 act = XDP_PASS;  in mtk_xdp_run()
2012 		u32 hash, reason;  in mtk_poll_rx()
2028 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);  in mtk_poll_rx()
2061 			u32 ret;  in mtk_poll_rx()
2263 	u32 cpu, dma;  in mtk_poll_tx_qdma()
2272 		u32 next_cpu = desc->txd2;  in mtk_poll_tx_qdma()
2312 	u32 cpu, dma;  in mtk_poll_tx_pdma()
2370 	u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);  in mtk_handle_status_irq()
2451 	u32 ofs, val;  in mtk_tx_alloc()
2476 		u32 next_ptr = ring->phys + next * sz;  in mtk_tx_alloc()
2510 	ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz));  in mtk_tx_alloc()
2776 	u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;  in mtk_hwlro_rx_init()
2777 	u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;  in mtk_hwlro_rx_init()
2836 	u32 val;  in mtk_hwlro_rx_uninit()
2861 	u32 reg_val;  in mtk_hwlro_val_ipaddr()
2876 	u32 reg_val;  in mtk_hwlro_inval_ipaddr()
2990 				  u32 *rule_locs)  in mtk_hwlro_get_fdir_all()
3043 	u32 val;  in mtk_dma_busy_wait()
3062 	u32 i;  in mtk_dma_init()
3143 	u32 val = mtk_r32(eth, MTK_INT_STATUS2);  in mtk_hw_reset_check()
3228 	u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;  in mtk_start_dma()
3265 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)  in mtk_gdm_config()
3273 		u32 val;  in mtk_gdm_config()
3367 		u32 gdm_config;  in mtk_open()
3417 		u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);  in mtk_open()
3428 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)  in mtk_stop_dma()
3430 	u32 val;  in mtk_stop_dma()
3531 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)  in ethsys_reset()
3577 	u32 val, cur;  in mtk_dim_rx()
3587 	cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);  in mtk_dim_rx()
3590 	cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);  in mtk_dim_rx()
3608 	u32 val, cur;  in mtk_dim_tx()
3618 	cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);  in mtk_dim_tx()
3621 	cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);  in mtk_dim_tx()
3633 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)  in mtk_set_mcr_max_rx()
3636 	u32 mcr_cur, mcr_new;  in mtk_set_mcr_max_rx()
3659 	u32 val;  in mtk_hw_reset()
3693 static u32 mtk_hw_reset_read(struct mtk_eth *eth)  in mtk_hw_reset_read()
3695 	u32 val;  in mtk_hw_reset_read()
3703 	u32 rst_mask, val;  in mtk_hw_warm_reset()
3754 	u32 wdidx, val, gdm1_fc, gdm2_fc;  in mtk_hw_check_dma_hang()
3846 	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |  in mtk_hw_init()
4077 	u32 val;  in mtk_prepare_for_reset()
4110 	u32 val;  in mtk_pending_work()
4258 static u32 mtk_get_msglevel(struct net_device *dev)  in mtk_get_msglevel()
4265 static void mtk_set_msglevel(struct net_device *dev, u32 value)  in mtk_set_msglevel()
4285 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)  in mtk_get_strings()
4371 			 u32 *rule_locs)  in mtk_get_rxnfc()
4488 	u32 val;  in mtk_add_mac()
4696 	u32 flags;  in mtk_sgmii_init()
4850 			u32 wdma_base;  in mtk_probe()
4946 		u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;  in mtk_probe()
4948 		num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);  in mtk_probe()
4950 			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;  in mtk_probe()