ethernet/mediatek/mtk_eth_soc.c

282 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
299 	mtk_w32(eth, val, reg);
328 	mtk_w32(eth, PHY_IAC_ACCESS |
352 	mtk_w32(eth, PHY_IAC_ACCESS |
364 	mtk_w32(eth, PHY_IAC_ACCESS |
387 	mtk_w32(eth, PHY_IAC_ACCESS |
410 	mtk_w32(eth, PHY_IAC_ACCESS |
422 	mtk_w32(eth, PHY_IAC_ACCESS |
487 		mtk_w32(eth, TRGMII_MODE, INTF_MODE);
590 					mtk_w32(mac->hw,
643 		mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
644 		mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
683 		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
696 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
765 	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
805 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
894 	mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
905 	mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
916 	mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
927 	mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
946 		mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
948 		mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
952 		mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
954 		mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
1178 	mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
1179 	mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
1180 	mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
1181 	mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
1508 			mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1514 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1670 		mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1676 				mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1874 		mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1879 		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
2304 	mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2378 		mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2391 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2424 		mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
2523 		mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2524 		mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2525 		mtk_w32(eth,
2528 		mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2532 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
2541 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
2545 		mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
2547 			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
2549 		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2550 		mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
2551 		mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2552 		mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2716 		mtk_w32(eth, ring->phys,
2718 		mtk_w32(eth, rx_dma_size,
2720 		mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2723 		mtk_w32(eth, ring->phys,
2725 		mtk_w32(eth, rx_dma_size,
2727 		mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2730 	mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2801 		mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2802 		mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2803 		mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2813 	mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2816 	mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2819 	mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2831 	mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2832 	mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2843 	mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2857 		mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2860 	mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2870 	mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2872 	mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2875 	mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2885 	mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2887 	mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
3109 		mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
3111 		mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
3254 		mtk_w32(eth, val, reg_map->qdma.glo_cfg);
3256 		mtk_w32(eth,
3261 		mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3295 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
3298 	mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
3299 	mtk_w32(eth, 0, MTK_RST_GL);
3424 		mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
3426 		mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
3440 	mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3597 	mtk_w32(eth, val, reg_map->pdma.delay_irq);
3599 		mtk_w32(eth, val, reg_map->qdma.delay_irq);
3628 	mtk_w32(eth, val, reg_map->pdma.delay_irq);
3630 		mtk_w32(eth, val, reg_map->qdma.delay_irq);
3658 		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3899 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
3923 		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3932 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
3935 		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
3937 		mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3949 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
3950 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
3951 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
3952 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
3953 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
3957 		mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
3961 		mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
3966 		mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
3971 		mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
3972 		mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
3973 		mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
3976 		mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
3977 		mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
3990 		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
3993 		mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0));
3996 		mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
3999 		mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
4000 		mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
4001 		mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
4002 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
4003 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
4004 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
4005 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
4006 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
4009 		mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
4010 		mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
4011 		mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
4012 		mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
4013 		mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
4014 		mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
4015 		mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
4016 		mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
4019 		mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
4020 		mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
4021 		mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
4022 		mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
4023 		mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
4024 		mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
4109 		mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4117 	mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
4122 		mtk_w32(eth, val, MTK_MAC_MCR(i));
4181 		mtk_w32(eth, val, MTK_FE_GLO_CFG(i));