Lines Matching +full:0 +full:x000e000e
35 module_param_named(msg_level, mtk_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
46 .tx_irq_mask = 0x1a1c,
47 .tx_irq_status = 0x1a18,
49 .rx_ptr = 0x0900,
50 .rx_cnt_cfg = 0x0904,
51 .pcrx_ptr = 0x0908,
52 .glo_cfg = 0x0a04,
53 .rst_idx = 0x0a08,
54 .delay_irq = 0x0a0c,
55 .irq_status = 0x0a20,
56 .irq_mask = 0x0a28,
57 .adma_rx_dbg0 = 0x0a38,
58 .int_grp = 0x0a50,
61 .qtx_cfg = 0x1800,
62 .qtx_sch = 0x1804,
63 .rx_ptr = 0x1900,
64 .rx_cnt_cfg = 0x1904,
65 .qcrx_ptr = 0x1908,
66 .glo_cfg = 0x1a04,
67 .rst_idx = 0x1a08,
68 .delay_irq = 0x1a0c,
69 .fc_th = 0x1a10,
70 .tx_sch_rate = 0x1a14,
71 .int_grp = 0x1a20,
72 .hred = 0x1a44,
73 .ctx_ptr = 0x1b00,
74 .dtx_ptr = 0x1b04,
75 .crx_ptr = 0x1b10,
76 .drx_ptr = 0x1b14,
77 .fq_head = 0x1b20,
78 .fq_tail = 0x1b24,
79 .fq_count = 0x1b28,
80 .fq_blen = 0x1b2c,
82 .gdm1_cnt = 0x2400,
83 .gdma_to_ppe = 0x4444,
84 .ppe_base = 0x0c00,
86 [0] = 0x2800,
87 [1] = 0x2c00,
89 .pse_iq_sta = 0x0110,
90 .pse_oq_sta = 0x0118,
94 .tx_irq_mask = 0x0a28,
95 .tx_irq_status = 0x0a20,
97 .rx_ptr = 0x0900,
98 .rx_cnt_cfg = 0x0904,
99 .pcrx_ptr = 0x0908,
100 .glo_cfg = 0x0a04,
101 .rst_idx = 0x0a08,
102 .delay_irq = 0x0a0c,
103 .irq_status = 0x0a20,
104 .irq_mask = 0x0a28,
105 .int_grp = 0x0a50,
110 .tx_irq_mask = 0x461c,
111 .tx_irq_status = 0x4618,
113 .rx_ptr = 0x6100,
114 .rx_cnt_cfg = 0x6104,
115 .pcrx_ptr = 0x6108,
116 .glo_cfg = 0x6204,
117 .rst_idx = 0x6208,
118 .delay_irq = 0x620c,
119 .irq_status = 0x6220,
120 .irq_mask = 0x6228,
121 .adma_rx_dbg0 = 0x6238,
122 .int_grp = 0x6250,
125 .qtx_cfg = 0x4400,
126 .qtx_sch = 0x4404,
127 .rx_ptr = 0x4500,
128 .rx_cnt_cfg = 0x4504,
129 .qcrx_ptr = 0x4508,
130 .glo_cfg = 0x4604,
131 .rst_idx = 0x4608,
132 .delay_irq = 0x460c,
133 .fc_th = 0x4610,
134 .int_grp = 0x4620,
135 .hred = 0x4644,
136 .ctx_ptr = 0x4700,
137 .dtx_ptr = 0x4704,
138 .crx_ptr = 0x4710,
139 .drx_ptr = 0x4714,
140 .fq_head = 0x4720,
141 .fq_tail = 0x4724,
142 .fq_count = 0x4728,
143 .fq_blen = 0x472c,
144 .tx_sch_rate = 0x4798,
146 .gdm1_cnt = 0x1c00,
147 .gdma_to_ppe = 0x3333,
148 .ppe_base = 0x2000,
150 [0] = 0x4800,
151 [1] = 0x4c00,
153 .pse_iq_sta = 0x0180,
154 .pse_oq_sta = 0x01a0,
158 .tx_irq_mask = 0x461c,
159 .tx_irq_status = 0x4618,
161 .rx_ptr = 0x6900,
162 .rx_cnt_cfg = 0x6904,
163 .pcrx_ptr = 0x6908,
164 .glo_cfg = 0x6a04,
165 .rst_idx = 0x6a08,
166 .delay_irq = 0x6a0c,
167 .irq_status = 0x6a20,
168 .irq_mask = 0x6a28,
169 .adma_rx_dbg0 = 0x6a38,
170 .int_grp = 0x6a50,
173 .qtx_cfg = 0x4400,
174 .qtx_sch = 0x4404,
175 .rx_ptr = 0x4500,
176 .rx_cnt_cfg = 0x4504,
177 .qcrx_ptr = 0x4508,
178 .glo_cfg = 0x4604,
179 .rst_idx = 0x4608,
180 .delay_irq = 0x460c,
181 .fc_th = 0x4610,
182 .int_grp = 0x4620,
183 .hred = 0x4644,
184 .ctx_ptr = 0x4700,
185 .dtx_ptr = 0x4704,
186 .crx_ptr = 0x4710,
187 .drx_ptr = 0x4714,
188 .fq_head = 0x4720,
189 .fq_tail = 0x4724,
190 .fq_count = 0x4728,
191 .fq_blen = 0x472c,
192 .tx_sch_rate = 0x4798,
194 .gdm1_cnt = 0x1c00,
195 .gdma_to_ppe = 0x3333,
196 .ppe_base = 0x2000,
198 [0] = 0x4800,
199 [1] = 0x4c00,
201 .pse_iq_sta = 0x0180,
202 .pse_oq_sta = 0x01a0,
309 return 0; in mtk_mdio_busy_wait()
325 if (ret < 0) in _mtk_mdio_write_c22()
337 if (ret < 0) in _mtk_mdio_write_c22()
340 return 0; in _mtk_mdio_write_c22()
349 if (ret < 0) in _mtk_mdio_write_c45()
361 if (ret < 0) in _mtk_mdio_write_c45()
373 if (ret < 0) in _mtk_mdio_write_c45()
376 return 0; in _mtk_mdio_write_c45()
384 if (ret < 0) in _mtk_mdio_read_c22()
395 if (ret < 0) in _mtk_mdio_read_c22()
407 if (ret < 0) in _mtk_mdio_read_c45()
419 if (ret < 0) in _mtk_mdio_read_c45()
430 if (ret < 0) in _mtk_mdio_read_c45()
473 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; in mt7621_gmac0_rgmii_adjust()
478 return 0; in mt7621_gmac0_rgmii_adjust()
500 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), in mtk_setup_bridge_switch()
521 0 : mac->id; in mtk_mac_select_pcs()
535 int val, ge_mode, err = 0; in mtk_mac_config()
589 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) in mtk_mac_config()
595 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, in mtk_mac_config()
597 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); in mtk_mac_config()
607 ge_mode = 0; in mtk_mac_config()
685 return 0; in mtk_mac_finish()
862 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); in mtk_mdio_init()
946 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
952 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
960 return 0; in mtk_set_mac_address()
983 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); in mtk_stats_update_mac()
987 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); in mtk_stats_update_mac()
989 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); in mtk_stats_update_mac()
991 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); in mtk_stats_update_mac()
993 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); in mtk_stats_update_mac()
995 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); in mtk_stats_update_mac()
997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); in mtk_stats_update_mac()
999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); in mtk_stats_update_mac()
1003 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); in mtk_stats_update_mac()
1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); in mtk_stats_update_mac()
1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); in mtk_stats_update_mac()
1008 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); in mtk_stats_update_mac()
1012 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); in mtk_stats_update_mac()
1015 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); in mtk_stats_update_mac()
1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); in mtk_stats_update_mac()
1019 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); in mtk_stats_update_mac()
1020 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); in mtk_stats_update_mac()
1024 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); in mtk_stats_update_mac()
1035 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_stats_update()
1159 for (i = 0; i < cnt; i++) { in mtk_init_fq_dma()
1169 txd->txd4 = 0; in mtk_init_fq_dma()
1171 txd->txd5 = 0; in mtk_init_fq_dma()
1172 txd->txd6 = 0; in mtk_init_fq_dma()
1173 txd->txd7 = 0; in mtk_init_fq_dma()
1174 txd->txd8 = 0; in mtk_init_fq_dma()
1183 return 0; in mtk_init_fq_dma()
1260 tx_buf->flags = 0; in mtk_tx_unmap()
1352 data = 0; in mtk_tx_set_dma_desc_v2()
1364 data = 0; in mtk_tx_set_dma_desc_v2()
1369 WRITE_ONCE(desc->txd7, 0); in mtk_tx_set_dma_desc_v2()
1370 WRITE_ONCE(desc->txd8, 0); in mtk_tx_set_dma_desc_v2()
1407 int k = 0; in mtk_tx_map()
1416 memset(itx_buf, 0, sizeof(*itx_buf)); in mtk_tx_map()
1434 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_tx_map()
1436 unsigned int offset = 0; in mtk_tx_map()
1443 (i & 0x1)) { in mtk_tx_map()
1454 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); in mtk_tx_map()
1471 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_tx_map()
1489 if (k & 0x1) in mtk_tx_map()
1517 return 0; in mtk_tx_map()
1543 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_cal_txd_req()
1559 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_queue_stopped()
1566 return 0; in mtk_queue_stopped()
1573 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_wake_queue()
1609 if (skb_cow_head(skb, 0)) { in mtk_start_xmit()
1622 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) in mtk_start_xmit()
1646 return ð->rx_ring[0]; in mtk_get_rx_ring()
1648 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { in mtk_get_rx_ring()
1669 ring = ð->rx_ring[0]; in mtk_update_rx_cpu_idx()
1672 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { in mtk_update_rx_cpu_idx()
1692 .order = 0, in mtk_create_page_pool()
1711 if (err < 0) in mtk_create_page_pool()
1784 return 0; in mtk_xdp_frame_map()
1800 int err, index = 0, n_desc = 1, nr_frags; in mtk_xdp_submit_frame()
1808 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; in mtk_xdp_submit_frame()
1822 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_xdp_submit_frame()
1828 if (err < 0) in mtk_xdp_submit_frame()
1834 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { in mtk_xdp_submit_frame()
1841 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_xdp_submit_frame()
1845 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); in mtk_xdp_submit_frame()
1885 return 0; in mtk_xdp_submit_frame()
1913 int i, nxmit = 0; in mtk_xdp_xmit()
1918 for (i = 0; i < num_frame; i++) { in mtk_xdp_xmit()
2003 u64 addr64 = 0; in mtk_poll_rx()
2006 int done = 0, bytes = 0; in mtk_poll_rx()
2013 int mac = 0; in mtk_poll_rx()
2046 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || in mtk_poll_rx()
2143 skb_set_hash(skb, jhash_1word(hash, 0), in mtk_poll_rx()
2150 skb_set_hash(skb, jhash_1word(hash, 0), in mtk_poll_rx()
2166 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); in mtk_poll_rx()
2174 mtk_ppe_check_skb(eth->ppe[0], skb, hash); in mtk_poll_rx()
2176 skb_record_rx_queue(skb, 0); in mtk_poll_rx()
2275 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) in mtk_poll_tx_qdma()
2325 mtk_poll_tx_done(eth, state, 0, tx_buf->data); in mtk_poll_tx_pdma()
2383 int tx_done = 0; in mtk_napi_tx()
2392 "done tx %d, intr 0x%08x/0x%x\n", tx_done, in mtk_napi_tx()
2413 int rx_done_total = 0; in mtk_napi_rx()
2427 "done rx %d, intr 0x%08x/0x%x\n", rx_done, in mtk_napi_rx()
2474 for (i = 0; i < ring_size; i++) { in mtk_tx_alloc()
2481 txd->txd4 = 0; in mtk_tx_alloc()
2483 txd->txd5 = 0; in mtk_tx_alloc()
2484 txd->txd6 = 0; in mtk_tx_alloc()
2485 txd->txd7 = 0; in mtk_tx_alloc()
2486 txd->txd8 = 0; in mtk_tx_alloc()
2500 for (i = 0; i < ring_size; i++) { in mtk_tx_alloc()
2502 ring->dma_pdma[i].txd4 = 0; in mtk_tx_alloc()
2526 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { in mtk_tx_alloc()
2547 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); in mtk_tx_alloc()
2551 return 0; in mtk_tx_alloc()
2564 for (i = 0; i < ring->dma_size; i++) in mtk_tx_clean()
2647 for (i = 0; i < rx_dma_size; i++) { in mtk_rx_alloc()
2687 rxd->rxd3 = 0; in mtk_rx_alloc()
2688 rxd->rxd4 = 0; in mtk_rx_alloc()
2690 rxd->rxd5 = 0; in mtk_rx_alloc()
2691 rxd->rxd6 = 0; in mtk_rx_alloc()
2692 rxd->rxd7 = 0; in mtk_rx_alloc()
2693 rxd->rxd8 = 0; in mtk_rx_alloc()
2728 return 0; in mtk_rx_alloc()
2733 u64 addr64 = 0; in mtk_rx_clean()
2737 for (i = 0; i < ring->dma_size; i++) { in mtk_rx_clean()
2776 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; in mtk_hwlro_rx_init()
2777 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; in mtk_hwlro_rx_init()
2819 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); in mtk_hwlro_rx_init()
2830 return 0; in mtk_hwlro_rx_init()
2842 for (i = 0; i < 10; i++) { in mtk_hwlro_rx_uninit()
2853 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); in mtk_hwlro_rx_uninit()
2856 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); in mtk_hwlro_rx_uninit()
2883 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); in mtk_hwlro_inval_ipaddr()
2888 int cnt = 0; in mtk_hwlro_get_ip_cnt()
2891 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_get_ip_cnt()
2920 return 0; in mtk_hwlro_add_ipaddr()
2935 mac->hwlro_ip[fsp->location] = 0; in mtk_hwlro_del_ipaddr()
2942 return 0; in mtk_hwlro_del_ipaddr()
2951 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_netdev_disable()
2952 mac->hwlro_ip[i] = 0; in mtk_hwlro_netdev_disable()
2958 mac->hwlro_ip_cnt = 0; in mtk_hwlro_netdev_disable()
2974 fsp->m_u.tcp_ip4_spec.ip4dst = 0; in mtk_hwlro_get_fdir_entry()
2976 fsp->h_u.tcp_ip4_spec.ip4src = 0; in mtk_hwlro_get_fdir_entry()
2977 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; in mtk_hwlro_get_fdir_entry()
2978 fsp->h_u.tcp_ip4_spec.psrc = 0; in mtk_hwlro_get_fdir_entry()
2979 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; in mtk_hwlro_get_fdir_entry()
2980 fsp->h_u.tcp_ip4_spec.pdst = 0; in mtk_hwlro_get_fdir_entry()
2981 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; in mtk_hwlro_get_fdir_entry()
2982 fsp->h_u.tcp_ip4_spec.tos = 0; in mtk_hwlro_get_fdir_entry()
2983 fsp->m_u.tcp_ip4_spec.tos = 0xff; in mtk_hwlro_get_fdir_entry()
2985 return 0; in mtk_hwlro_get_fdir_entry()
2993 int cnt = 0; in mtk_hwlro_get_fdir_all()
2996 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_get_fdir_all()
3008 return 0; in mtk_hwlro_get_fdir_all()
3035 return 0; in mtk_set_features()
3081 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); in mtk_dma_init()
3086 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); in mtk_dma_init()
3107 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); in mtk_dma_init()
3110 return 0; in mtk_dma_init()
3118 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_dma_free()
3126 eth->phy_scratch_ring = 0; in mtk_dma_free()
3129 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); in mtk_dma_free()
3228 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; in mtk_start_dma()
3262 return 0; in mtk_start_dma()
3272 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_gdm_config()
3281 val &= ~0xffff; in mtk_gdm_config()
3295 mtk_w32(eth, 0, MTK_RST_GL); in mtk_gdm_config()
3336 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) in mtk_device_event()
3343 if (mac->speed > 0 && mac->speed <= s.base.speed) in mtk_device_event()
3344 s.base.speed = 0; in mtk_device_event()
3357 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); in mtk_open()
3376 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_open()
3396 return 0; in mtk_open()
3399 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_open()
3405 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, in mtk_open()
3422 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); in mtk_open()
3425 return 0; in mtk_open()
3441 for (i = 0; i < 10; i++) { in mtk_stop_dma()
3465 return 0; in mtk_stop()
3483 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_stop()
3486 return 0; in mtk_stop()
3518 return 0; in mtk_xdp_setup()
3548 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) in mtk_clk_disable()
3556 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { in mtk_clk_enable()
3562 return 0; in mtk_clk_enable()
3565 while (--clk >= 0) in mtk_clk_enable()
3662 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3687 0x6f8ff); in mtk_hw_reset()
3690 0x3ffffff); in mtk_hw_reset()
3762 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); in mtk_hw_check_dma_hang()
3764 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); in mtk_hw_check_dma_hang()
3767 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); in mtk_hw_check_dma_hang()
3771 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && in mtk_hw_check_dma_hang()
3772 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); in mtk_hw_check_dma_hang()
3776 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3783 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); in mtk_hw_check_dma_hang()
3784 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); in mtk_hw_check_dma_hang()
3786 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; in mtk_hw_check_dma_hang()
3787 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; in mtk_hw_check_dma_hang()
3788 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; in mtk_hw_check_dma_hang()
3790 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); in mtk_hw_check_dma_hang()
3791 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); in mtk_hw_check_dma_hang()
3797 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3804 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); in mtk_hw_check_dma_hang()
3806 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && in mtk_hw_check_dma_hang()
3811 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3817 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3818 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3819 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3852 return 0; in mtk_hw_init()
3879 mtk_tx_irq_disable(eth, ~0); in mtk_hw_init()
3880 mtk_rx_irq_disable(eth, ~0); in mtk_hw_init()
3882 return 0; in mtk_hw_init()
3900 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); in mtk_hw_init()
3903 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); in mtk_hw_init()
3906 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); in mtk_hw_init()
3913 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_hw_init()
3941 mtk_tx_irq_disable(eth, ~0); in mtk_hw_init()
3942 mtk_rx_irq_disable(eth, ~0); in mtk_hw_init()
3949 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); in mtk_hw_init()
3953 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); in mtk_hw_init()
3956 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); in mtk_hw_init()
3957 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); in mtk_hw_init()
3960 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); in mtk_hw_init()
3966 for (i = 0; i < 0x80; i += 0x4) in mtk_hw_init()
3967 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); in mtk_hw_init()
3970 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); in mtk_hw_init()
3973 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); in mtk_hw_init()
3976 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); in mtk_hw_init()
3979 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); in mtk_hw_init()
3980 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); in mtk_hw_init()
3981 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); in mtk_hw_init()
3982 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); in mtk_hw_init()
3983 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); in mtk_hw_init()
3984 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); in mtk_hw_init()
3985 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); in mtk_hw_init()
3986 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); in mtk_hw_init()
3989 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); in mtk_hw_init()
3990 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); in mtk_hw_init()
3991 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); in mtk_hw_init()
3992 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); in mtk_hw_init()
3993 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); in mtk_hw_init()
3994 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); in mtk_hw_init()
3995 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); in mtk_hw_init()
3996 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); in mtk_hw_init()
3999 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); in mtk_hw_init()
4000 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); in mtk_hw_init()
4001 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); in mtk_hw_init()
4002 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); in mtk_hw_init()
4003 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); in mtk_hw_init()
4004 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); in mtk_hw_init()
4007 return 0; in mtk_hw_init()
4021 return 0; in mtk_hw_deinit()
4028 return 0; in mtk_hw_deinit()
4037 mtk_tx_irq_disable(eth, ~0); in mtk_uninit()
4038 mtk_rx_irq_disable(eth, ~0); in mtk_uninit()
4056 return 0; in mtk_change_mtu()
4093 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_prepare_for_reset()
4097 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); in mtk_prepare_for_reset()
4100 for (i = 0; i < 2; i++) { in mtk_prepare_for_reset()
4109 unsigned long restart = 0; in mtk_pending_work()
4124 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_pending_work()
4140 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_pending_work()
4175 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_free_dev()
4181 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_free_dev()
4187 return 0; in mtk_free_dev()
4194 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_unreg_dev()
4204 return 0; in mtk_unreg_dev()
4211 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_sgmii_destroy()
4223 return 0; in mtk_cleanup()
4293 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { in mtk_get_strings()
4327 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { in mtk_ethtool_pp_stats()
4363 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) in mtk_get_ethtool_stats()
4379 ret = 0; in mtk_get_rxnfc()
4387 ret = 0; in mtk_get_rxnfc()
4430 unsigned int queue = 0; in mtk_select_queue()
4438 queue = 0; in mtk_select_queue()
4531 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); in mtk_add_mac()
4532 mac->hwlro_ip_cnt = 0; in mtk_add_mac()
4546 mac->hw_stats->reg_offset = id * 0x80; in mtk_add_mac()
4548 mac->hw_stats->reg_offset = id * 0x40; in mtk_add_mac()
4570 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { in mtk_add_mac()
4637 eth->netdev[id]->irq = eth->irq[0]; in mtk_add_mac()
4656 return 0; in mtk_add_mac()
4671 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_eth_set_dma_device()
4699 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_sgmii_init()
4705 flags = 0; in mtk_sgmii_init()
4719 return 0; in mtk_sgmii_init()
4737 eth->base = devm_platform_ioremap_resource(pdev, 0); in mtk_probe()
4806 regmap_write(cci, 0, 3); in mtk_probe()
4827 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mtk_probe()
4847 for (i = 0;; i++) { in mtk_probe()
4861 wdma_phy = res ? res->start + wdma_base : 0; in mtk_probe()
4867 for (i = 0; i < 3; i++) { in mtk_probe()
4868 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) in mtk_probe()
4869 eth->irq[i] = eth->irq[0]; in mtk_probe()
4872 if (eth->irq[i] < 0) { in mtk_probe()
4878 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { in mtk_probe()
4921 err = devm_request_irq(eth->dev, eth->irq[0], in mtk_probe()
4922 mtk_handle_irq, 0, in mtk_probe()
4926 mtk_handle_irq_tx, 0, in mtk_probe()
4932 mtk_handle_irq_rx, 0, in mtk_probe()
4949 for (i = 0; i < num_ppe; i++) { in mtk_probe()
4950 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; in mtk_probe()
4965 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_probe()
4975 "mediatek frame engine at 0x%08lx, irq %d\n", in mtk_probe()
4976 eth->netdev[i]->base_addr, eth->irq[0]); in mtk_probe()
4990 return 0; in mtk_probe()
5014 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_remove()
5030 return 0; in mtk_remove()
5072 .ana_rgc3 = 0x2028,
5115 .ana_rgc3 = 0x128,
5134 .ana_rgc3 = 0x128,
5156 .ana_rgc3 = 0x128,
5178 .ana_rgc3 = 0x128,