1142 	struct npc_mcam_write_entry_req write_req = { 0 };  in npc_install_flow()  local
1155 	entry = &write_req.entry_data;  in npc_install_flow()
1208 	write_req.hdr.pcifunc = owner;  in npc_install_flow()
1214 		write_req.hdr.pcifunc = 0;  in npc_install_flow()
1216 	write_req.entry = entry_index;  in npc_install_flow()
1217 	write_req.intf = req->intf;  in npc_install_flow()
1218 	write_req.enable_entry = (u8)enable;  in npc_install_flow()
1222 		write_req.set_cntr = 1;  in npc_install_flow()
1223 		write_req.cntr = rule->cntr;  in npc_install_flow()
1239 	rule->chan_mask = write_req.entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;  in npc_install_flow()
1240 	rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK;  in npc_install_flow()
1254 	err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req,  in npc_install_flow()
1486 	struct npc_mcam_write_entry_req write_req = { 0 };  in npc_update_dmac_value()  local
1487 	struct mcam_entry *entry = &write_req.entry_data;  in npc_update_dmac_value()
1502 	write_req.hdr.pcifunc = rule->owner;  in npc_update_dmac_value()
1503 	write_req.entry = rule->entry;  in npc_update_dmac_value()
1504 	write_req.intf = pfvf->nix_rx_intf;  in npc_update_dmac_value()
1507 	err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, &rsp);  in npc_update_dmac_value()