Lines Matching +full:comp +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0
66 #define is_rev_A0(ptp) (((ptp)->pdev->revision & 0x0F) == 0x0)
67 #define is_rev_A1(ptp) (((ptp)->pdev->revision & 0x0F) == 0x1)
81 return ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A_PTP; in is_ptp_dev_cnf10ka()
86 return ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_PTP; in is_ptp_dev_cn10ka()
100 struct ptp *ptp = rvu->ptp; in is_tstmp_atomic_update_supported()
123 delta_ns = ktime_to_ns(ktime_sub(curr_ts, ptp->last_ts)); in ptp_reset_thresh()
129 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); in ptp_reset_thresh()
131 period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - ptp_clock_hi)); in ptp_reset_thresh()
133 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_reset_thresh()
134 period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - delta_ns)); in ptp_reset_thresh()
138 ptp->last_ts = curr_ts; in ptp_reset_thresh()
147 period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - start_ns)); in ptp_hrtimer_start()
148 hrtimer_start(&ptp->hrtimer, period_ns, HRTIMER_MODE_REL); in ptp_hrtimer_start()
149 ptp->last_ts = ktime_get(); in ptp_hrtimer_start()
157 spin_lock_irqsave(&ptp->ptp_lock, flags); in read_ptp_tstmp_sec_nsec()
158 sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
159 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
160 sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
163 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
166 spin_unlock_irqrestore(&ptp->ptp_lock, flags); in read_ptp_tstmp_sec_nsec()
173 return readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_nsec()
178 u64 comp, adj = 0, cycles_per_sec, ns_drift = 0; in ptp_calc_adjusted_comp() local
183 * Issue #1: At the time of 1 sec rollover of the nano-second counter, in ptp_calc_adjusted_comp()
184 * the nano-second counter is set to 0. However, it should be set to in ptp_calc_adjusted_comp()
185 * (existing counter_value - 10^9). in ptp_calc_adjusted_comp()
187 * Issue #2: The nano-second counter rolls over at 0x3B9A_C9FF. in ptp_calc_adjusted_comp()
192 comp = ((u64)1000000000ULL << 32) / ptp_clock_freq; in ptp_calc_adjusted_comp()
199 cycle = cycles_per_sec - 1; in ptp_calc_adjusted_comp()
200 ptp_clock_nsec = (cycle * comp) >> 32; in ptp_calc_adjusted_comp()
205 ptp_clock_nsec = (cycle * comp) >> 32; in ptp_calc_adjusted_comp()
208 ns_drift = ptp_clock_nsec - NSEC_PER_SEC; in ptp_calc_adjusted_comp()
211 adj = comp * ns_drift; in ptp_calc_adjusted_comp()
215 comp += adj; in ptp_calc_adjusted_comp()
216 return comp; in ptp_calc_adjusted_comp()
220 adj = comp * cycle_time; in ptp_calc_adjusted_comp()
223 comp -= adj; in ptp_calc_adjusted_comp()
225 return comp; in ptp_calc_adjusted_comp()
234 return ERR_PTR(-ENODEV); in ptp_get()
237 ptp = ERR_PTR(-EPROBE_DEFER); in ptp_get()
239 pci_dev_get(ptp->pdev); in ptp_get()
249 pci_dev_put(ptp->pdev); in ptp_put()
257 writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_atomic_update()
258 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update()
260 ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_atomic_update()
263 curr_rollover_set = nxt_rollover_set - NSEC_PER_SEC; in ptp_atomic_update()
264 writeq(nxt_rollover_set, ptp->reg_base + PTP_NXT_ROLLOVER_SET); in ptp_atomic_update()
265 writeq(curr_rollover_set, ptp->reg_base + PTP_CURR_ROLLOVER_SET); in ptp_atomic_update()
268 regval = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update()
271 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update()
280 delta = -delta; in ptp_atomic_adjtime()
289 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); in ptp_atomic_adjtime()
292 ptp_clock_hi -= delta; in ptp_atomic_adjtime()
294 ptp_clock_hi = delta - ptp_clock_hi; in ptp_atomic_adjtime()
300 writeq(delta, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_atomic_adjtime()
301 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_adjtime()
304 regval = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_adjtime()
307 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_adjtime()
315 u64 comp, adj; in ptp_adjfine() local
320 scaled_ppm = -scaled_ppm; in ptp_adjfine()
326 * convention compensation value is in 64 bit fixed-point in ptp_adjfine()
333 * comp = tbase + tbase * scaled_ppm / (1M * 2^16) in ptp_adjfine()
344 freq_adj = (ptp->clock_rate * ppb) / 1000000000ULL; in ptp_adjfine()
345 freq = neg_adj ? ptp->clock_rate + freq_adj : ptp->clock_rate - freq_adj; in ptp_adjfine()
346 comp = ptp_calc_adjusted_comp(freq); in ptp_adjfine()
348 comp = ((u64)1000000000ull << 32) / ptp->clock_rate; in ptp_adjfine()
349 adj = comp * ppb; in ptp_adjfine()
351 comp = neg_adj ? comp - adj : comp + adj; in ptp_adjfine()
353 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine()
361 *clk = ptp->read_ptp_tstmp(ptp); in ptp_get_clock()
368 struct ptp *ptp = rvu->ptp; in ptp_start()
376 pdev = ptp->pdev; in ptp_start()
379 dev_err(&pdev->dev, "PTP input clock cannot be zero\n"); in ptp_start()
384 ptp->clock_rate = sclk * 1000000; in ptp_start()
388 writeq(0, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_start()
389 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_start()
390 writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_start()
391 writeq(0, ptp->reg_base + PTP_CURR_ROLLOVER_SET); in ptp_start()
392 writeq(0x3b9aca00, ptp->reg_base + PTP_NXT_ROLLOVER_SET); in ptp_start()
393 writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER); in ptp_start()
397 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
400 ptp->clock_rate = ext_clk_freq; in ptp_start()
415 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
416 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
419 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
422 writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_HI_INCR); in ptp_start()
423 writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_LO_INCR); in ptp_start()
432 ptp->clock_period = NSEC_PER_SEC / ptp->clock_rate; in ptp_start()
433 writeq((0x1dcd6500ULL - ptp->clock_period) << 32, in ptp_start()
434 ptp->reg_base + PTP_PPS_LO_INCR); in ptp_start()
438 clock_comp = ptp_calc_adjusted_comp(ptp->clock_rate); in ptp_start()
440 clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate; in ptp_start()
443 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_start()
451 timestamp = readq(ptp->reg_base + PTP_TIMESTAMP); in ptp_get_tstmp()
454 *clk = readq(ptp->reg_base + PTP_TIMESTAMP); in ptp_get_tstmp()
463 writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_set_thresh()
474 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); in ptp_extts_on()
477 if (hrtimer_active(&ptp->hrtimer)) in ptp_extts_on()
478 hrtimer_cancel(&ptp->hrtimer); in ptp_extts_on()
493 err = -ENOMEM; in ptp_probe()
497 ptp->pdev = pdev; in ptp_probe()
507 ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO]; in ptp_probe()
513 spin_lock_init(&ptp->ptp_lock); in ptp_probe()
515 ptp->read_ptp_tstmp = &read_ptp_tstmp_sec_nsec; in ptp_probe()
516 hrtimer_init(&ptp->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in ptp_probe()
517 ptp->hrtimer.function = ptp_reset_thresh; in ptp_probe()
519 ptp->read_ptp_tstmp = &read_ptp_tstmp_nsec; in ptp_probe()
531 * `dev->driver_data`. in ptp_probe()
548 if (cn10k_ptp_errata(ptp) && hrtimer_active(&ptp->hrtimer)) in ptp_remove()
549 hrtimer_cancel(&ptp->hrtimer); in ptp_remove()
551 /* Disable PTP clock */ in ptp_remove()
552 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_remove()
554 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_remove()
600 if (!rvu->ptp) in rvu_mbox_handler_ptp_op()
601 return -ENODEV; in rvu_mbox_handler_ptp_op()
603 switch (req->op) { in rvu_mbox_handler_ptp_op()
605 err = ptp_adjfine(rvu->ptp, req->scaled_ppm); in rvu_mbox_handler_ptp_op()
608 err = ptp_get_clock(rvu->ptp, &rsp->clk); in rvu_mbox_handler_ptp_op()
611 err = ptp_get_tstmp(rvu->ptp, &rsp->clk); in rvu_mbox_handler_ptp_op()
614 err = ptp_set_thresh(rvu->ptp, req->thresh); in rvu_mbox_handler_ptp_op()
617 err = ptp_extts_on(rvu->ptp, req->extts_on); in rvu_mbox_handler_ptp_op()
620 ptp_atomic_adjtime(rvu->ptp, req->delta); in rvu_mbox_handler_ptp_op()
623 ptp_atomic_update(rvu->ptp, (u64)req->clk); in rvu_mbox_handler_ptp_op()
626 err = -EINVAL; in rvu_mbox_handler_ptp_op()
636 if (!rvu->ptp) in rvu_mbox_handler_ptp_get_cap()
637 return -ENODEV; in rvu_mbox_handler_ptp_get_cap()
640 rsp->cap |= PTP_CAP_HW_ATOMIC_UPDATE; in rvu_mbox_handler_ptp_get_cap()
642 rsp->cap &= ~BIT_ULL_MASK(0); in rvu_mbox_handler_ptp_get_cap()