Lines Matching refs:u8
433 u8 modify:1;
434 u8 npalf:1;
435 u8 nixlf:1;
450 u8 partial:1;
451 u8 npalf:1;
452 u8 nixlf:1;
453 u8 sso:1;
454 u8 ssow:1;
455 u8 timlfs:1;
456 u8 cptlfs:1;
469 u8 npa;
470 u8 nix;
472 u8 nix1;
473 u8 cpt1;
474 u8 ree0;
475 u8 ree1;
503 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
504 u8 nix_shaping; /* Is shaping and coloring supported */
505 u8 npc_hash_extract; /* Is hash extract supported */
528 u8 mac_addr[ETH_ALEN];
537 u8 mac_addr[ETH_ALEN];
582 u8 set;
585 u8 rx_pause;
586 u8 tx_pause;
605 u8 buf[SFP_EEPROM_SIZE];
645 u8 duplex;
646 u8 an;
647 u8 ports;
669 u8 mac_addr[ETH_ALEN];
702 u8 rx_pause;
703 u8 tx_pause;
709 u8 rx_pause;
710 u8 tx_pause;
722 u8 dir;
723 u8 pkind; /* valid only in case custom flag */
724 u8 var_len_off; /* Offset of custom header length field.
727 u8 var_len_off_mask; /* Mask for length with in offset */
728 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
759 u8 cache_lines; /*BATCH ALLOC DMA */
766 u8 ctype;
767 u8 op;
799 u8 ctype;
860 u8 xqe_sz;
862 u8 rss_grps;
877 u8 rx_chan_cnt; /* total number of RX channels */
878 u8 tx_chan_cnt; /* total number of TX channels */
879 u8 lso_tsov4_idx;
880 u8 lso_tsov6_idx;
881 u8 mac_addr[ETH_ALEN];
882 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
883 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
886 u8 cgx_links; /* No. of CGX links present in HW */
887 u8 lbk_links; /* No. of LBK links present in HW */
888 u8 sdp_links; /* No. of SDP links present in HW */
889 u8 tx_link; /* Transmit channel link number */
903 u8 ctype;
904 u8 op;
939 u8 ctype;
940 u8 op;
990 u8 aggr_level; /* Traffic aggregation scheduler level */
991 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
992 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
1007 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1008 u8 read;
1012 u8 num_regs;
1023 u8 vtag_size;
1027 u8 cfg_type;
1038 u8 cfg_vtag0 :1;
1040 u8 cfg_vtag1 :1;
1060 u8 free_vtag0 :1;
1064 u8 free_vtag1 :1;
1070 u8 vtag_type;
1072 u8 strip_vtag :1;
1074 u8 capture_vtag :1;
1122 u8 group; /* RSS context or group */
1127 u8 alg_idx; /* Selected algo index */
1132 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1137 u8 mac_addr[ETH_ALEN];
1142 u8 offset;
1143 u8 y_mask;
1144 u8 y_val;
1145 u8 r_mask;
1146 u8 r_val;
1151 u8 mark_format_idx;
1168 u8 len_verify; /* Outer L3/L4 len check */
1170 u8 csum_verify; /* Outer L4 checksum verification */
1175 u8 update_smq; /* Update SMQ's min/max lens */
1176 u8 update_minlen; /* Set minlen also */
1177 u8 sdp_link; /* Set SDP RX link */
1191 u8 lso_format_idx;
1197 u8 chan_cnt; /* Number of channels */
1198 u8 bpid_per_chan;
1210 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1218 u8 egrp;
1225 u8 cpt_slot;
1227 u8 enable;
1239 u8 sa_pow2_size;
1240 u8 tt;
1244 u8 sa_idx_w;
1246 u8 enable;
1281 u8 free_all;
1317 u8 contig; /* Contiguous entries ? */
1321 u8 priority; /* Lower or higher w.r.t ref_entry */
1339 u8 all; /* If all entries allocated to this PFVF to be freed */
1355 u8 intf; /* Rx or Tx interface */
1356 u8 enable_entry;/* Enable this MCAM entry ? */
1357 u8 set_cntr; /* Set counter for this entry ? */
1381 u8 contig; /* Contiguous counters ? */
1409 u8 all; /* Unmap all entries using this counter ? */
1416 u8 priority; /* Lower or higher w.r.t ref_entry */
1417 u8 intf; /* Rx or Tx interface */
1418 u8 enable_entry;/* Enable this MCAM entry ? */
1419 u8 alloc_cntr; /* Allocate counter and map ? */
1444 u8 mkex_pfl_name[MKEX_NAME_LEN];
1471 u8 tos;
1472 u8 ip_ver;
1473 u8 ip_proto;
1474 u8 tc;
1478 u8 ip_flag;
1479 u8 next_header;
1492 u8 intf;
1493 u8 set_cntr; /* If counter is available set counter for this entry ? */
1494 u8 default_rule;
1495 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1500 u8 flow_key_alg;
1501 u8 op;
1503 u8 vtag0_type;
1504 u8 vtag0_valid;
1505 u8 vtag1_type;
1506 u8 vtag1_valid;
1509 u8 vtag0_op;
1511 u8 vtag1_op;
1526 u8 all; /* PF + VFs */
1542 u8 intf;
1543 u8 enable;
1559 u8 stat_ena; /* enabled */
1564 u8 intf;
1590 u8 op;
1606 u8 intf;
1607 u8 field;
1612 u8 enable;
1630 u8 use_local_lmt_region;
1655 u8 is_write;
1664 u8 blkaddr;
1665 u8 ctx_ilen_valid : 1;
1666 u8 ctx_ilen : 7;
1677 u8 enable;
1678 u8 slot;
1679 u8 dir;
1680 u8 sso_pf_func_ovrd;
1688 u8 blkaddr;
1774 u8 node_id;
1775 u8 max_vfs;
1776 u8 num_pf_rings;
1777 u8 pf_srn;
1779 u8 vf_rings[SDP_MAX_VFS];
1823 u8 rsrc_type;
1824 u8 rsrc_cnt; /* Resources count */
1825 u8 mcs_id; /* MCS block ID */
1826 u8 dir; /* Macsec ingress or egress side */
1827 u8 all; /* Allocate all resource type one each */
1833 u8 flow_ids[128]; /* Index of reserved entries */
1834 u8 secy_ids[128];
1835 u8 sc_ids[128];
1836 u8 sa_ids[256];
1837 u8 rsrc_type;
1838 u8 rsrc_cnt; /* No of entries reserved */
1839 u8 mcs_id;
1840 u8 dir;
1841 u8 all;
1842 u8 rsvd[256]; /* reserved fields for future expansion */
1847 u8 rsrc_id; /* Index of the entry to be freed */
1848 u8 rsrc_type;
1849 u8 mcs_id;
1850 u8 dir;
1851 u8 all; /* Free all the cam resources */
1860 u8 flow_id;
1861 u8 secy_id; /* secyid for which flowid is mapped */
1862 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
1863 u8 ena; /* Enable tcam entry */
1864 u8 ctrl_pkt;
1865 u8 mcs_id;
1866 u8 dir;
1873 u8 secy_id;
1874 u8 mcs_id;
1875 u8 dir;
1884 u8 sc_id; /* SC CAM entry index */
1885 u8 mcs_id;
1892 u8 sa_index[2];
1893 u8 sa_cnt;
1894 u8 mcs_id;
1895 u8 dir;
1901 u8 sa_index0;
1902 u8 sa_index1;
1903 u8 rekey_ena;
1904 u8 sa_index0_vld;
1905 u8 sa_index1_vld;
1906 u8 tx_sa_active;
1908 u8 sc_id; /* used as index for SA_MEM_MAP */
1909 u8 mcs_id;
1915 u8 sa_index;
1916 u8 sa_in_use;
1917 u8 sc_id;
1918 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
1919 u8 mcs_id;
1925 u8 flow_id;
1926 u8 ena;
1927 u8 mcs_id;
1928 u8 dir;
1935 u8 pn_id;
1936 u8 mcs_id;
1937 u8 dir;
1943 u8 num_mcs_blks; /* Number of MCS blocks */
1944 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
1945 u8 secy_entries; /* RX/TX SECY entries per mcs block */
1946 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
1954 u8 mcs_id;
1961 u8 mode; /* 1:Bypass 0:Operational */
1962 u8 lmac_id;
1963 u8 mcs_id;
1969 u8 reset;
1970 u8 mcs_id;
1971 u8 port_id;
1977 u8 cstm_tag_rel_mode_sel;
1978 u8 custom_hdr_enb;
1979 u8 fifo_skid;
1980 u8 port_mode;
1981 u8 port_id;
1982 u8 mcs_id;
1988 u8 port_id;
1989 u8 mcs_id;
1995 u8 cstm_tag_rel_mode_sel;
1996 u8 custom_hdr_enb;
1997 u8 fifo_skid;
1998 u8 port_mode;
1999 u8 port_id;
2000 u8 mcs_id;
2006 u8 mcs_id;
2007 u8 dir;
2014 u8 cstm_indx[8];
2015 u8 cstm_etype_en;
2016 u8 mcs_id;
2017 u8 dir;
2032 u8 xpn; /* '1' for setting xpn threshold */
2033 u8 mcs_id;
2034 u8 dir;
2048 u8 rule_type;
2049 u8 mcs_id; /* MCS block ID */
2050 u8 dir; /* Macsec ingress or egress side */
2056 u8 rule_idx;
2057 u8 rule_type;
2058 u8 mcs_id;
2059 u8 dir;
2065 u8 rule_idx;
2066 u8 rule_type;
2067 u8 mcs_id;
2068 u8 dir;
2069 u8 all;
2078 u8 rule_idx;
2079 u8 rule_type;
2080 u8 mcs_id;
2081 u8 dir;
2087 u8 id;
2088 u8 mcs_id;
2089 u8 dir;
2180 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2181 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2182 u8 mcs_id;
2183 u8 dir;
2184 u8 all; /* All resources stats mapped to PF are cleared */
2206 u8 mcs_id;
2207 u8 lmac_id;
2215 u8 mcs_id;
2216 u8 lmac_id;