293 #define	   CN93_SDP_EPF_MBOX_RINT(index)		\  argument
294 		(CN93_SDP_EPF_MBOX_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET))
295 #define	   CN93_SDP_EPF_MBOX_RINT_W1S(index)		\  argument
296 		(CN93_SDP_EPF_MBOX_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET))
297 #define	   CN93_SDP_EPF_MBOX_RINT_ENA_W1C(index)	\  argument
298 		(CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET))
299 #define	   CN93_SDP_EPF_MBOX_RINT_ENA_W1S(index)	\  argument
300 		(CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET))
302 #define	   CN93_SDP_EPF_VFIRE_RINT(index)		\  argument
303 		(CN93_SDP_EPF_VFIRE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET))
304 #define	   CN93_SDP_EPF_VFIRE_RINT_W1S(index)		\  argument
305 		(CN93_SDP_EPF_VFIRE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET))
306 #define	   CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(index)	\  argument
307 		(CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET))
308 #define	   CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(index)	\  argument
309 		(CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET))
311 #define	   CN93_SDP_EPF_VFORE_RINT(index)		\  argument
312 		(CN93_SDP_EPF_VFORE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET))
313 #define	   CN93_SDP_EPF_VFORE_RINT_W1S(index)		\  argument
314 		(CN93_SDP_EPF_VFORE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET))
315 #define	   CN93_SDP_EPF_VFORE_RINT_ENA_W1C(index)	\  argument
316 		(CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET))
317 #define	   CN93_SDP_EPF_VFORE_RINT_ENA_W1S(index)	\  argument
318 		(CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET))
320 #define	   CN93_SDP_EPF_DMA_VF_RINT(index)		\  argument
321 		(CN93_SDP_EPF_DMA_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET))
322 #define	   CN93_SDP_EPF_DMA_VF_RINT_W1S(index)		\  argument
323 		(CN93_SDP_EPF_DMA_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET))
324 #define	   CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(index)	\  argument
325 		(CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET))
326 #define	   CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(index)	\  argument
327 		(CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET))
329 #define	   CN93_SDP_EPF_PP_VF_RINT(index)		\  argument
330 		(CN93_SDP_EPF_PP_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET))
331 #define	   CN93_SDP_EPF_PP_VF_RINT_W1S(index)		\  argument
332 		(CN93_SDP_EPF_PP_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET))
333 #define	   CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(index)	\  argument
334 		(CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET))
335 #define	   CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(index)	\  argument
336 		(CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET))