74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)  in mvpp2_write()
79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)  in mvpp2_read()
84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)  in mvpp2_read_relaxed()
89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)  in mvpp2_cpu_to_thread()
94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)  in mvpp2_cm3_write()
99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)  in mvpp2_cm3_read()
159 			       u32 offset, u32 data)  in mvpp2_thread_write()
164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,  in mvpp2_thread_read()
165 			     u32 offset)  in mvpp2_thread_read()
171 				       u32 offset, u32 data)  in mvpp2_thread_write_relaxed()
176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,  in mvpp2_thread_read_relaxed()
177 				     u32 offset)  in mvpp2_thread_read_relaxed()
290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,  in mvpp2_rxdesc_status_get()
389 	u32 val;  in mvpp2_bm_pool_create()
401 		bm_pool->size_bytes = 2 * sizeof(u32) * size;  in mvpp2_bm_pool_create()
453 	u32 val;  in mvpp2_bm_pool_bufsize_set()
473 		u32 val;  in mvpp2_bm_bufs_get_addrs()
474 		u32 dma_addr_highbits, phys_addr_highbits;  in mvpp2_bm_bufs_get_addrs()
552 	u32 val;  in mvpp2_bm_pool_destroy()
621 	u32 val;  in mvpp2_bm_pool_cleanup()
723 	u32 val, mask;  in mvpp2_rxq_long_pool_set()
744 	u32 val, mask;  in mvpp2_rxq_short_pool_set()
1011 		u32 val = 0;  in mvpp2_bm_pool_put()
1431 	u32 thread;  in mvpp2_interrupts_mask()
1453 	u32 val, thread;  in mvpp2_interrupts_unmask()
1476 	u32 val;  in mvpp2_shared_interrupt_mask_unmask()
1520 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)  in mvpp2_modify()
1522 	u32 old, val;  in mvpp2_modify()
1534 	u32 val;  in mvpp22_gop_init_rgmii()
1551 	u32 val;  in mvpp22_gop_init_sgmii()
1573 	u32 val;  in mvpp22_gop_init_10gkr()
1595 	u32 val;  in mvpp22_gop_fca_enable_periodic()
1604 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)  in mvpp22_gop_fca_set_timer()
1608 	u32 lsb, msb;  in mvpp22_gop_fca_set_timer()
1622 	u32 timer;  in mvpp22_gop_fca_set_periodic_timer()
1637 	u32 val;  in mvpp22_gop_init()
1691 	u32 val;  in mvpp22_gop_unmask_irq()
1715 	u32 val;  in mvpp22_gop_mask_irq()
1735 	u32 val;  in mvpp22_gop_setup_irq()
1790 	u32 val;  in mvpp2_port_enable()
1808 	u32 val;  in mvpp2_port_disable()
1825 	u32 val;  in mvpp2_port_periodic_xon_disable()
1836 	u32 val;  in mvpp2_port_loopback_set()
1887 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)  in mvpp2_read_index()
1972 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,  in mvpp2_ethtool_get_strings()
2168 	u32 val;  in mvpp2_mac_reset_assert()
2185 	u32 val;  in mvpp22_pcs_reset_assert()
2207 	u32 val;  in mvpp22_pcs_reset_deassert()
2237 	u32 val;  in mvpp2_gmac_max_rx_size_set()
2249 	u32 val;  in mvpp2_xlg_max_rx_size_set()
2320 	u32 val;  in mvpp2_ingress_enable()
2333 	u32 val;  in mvpp2_ingress_disable()
2349 	u32 qmap;  in mvpp2_egress_enable()
2371 	u32 reg_data;  in mvpp2_egress_disable()
2408 	u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));  in mvpp2_rxq_received()
2423 	u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);  in mvpp2_rxq_status_update()
2443 	u32 val;  in mvpp2_rxq_offset_set()
2496 		u32 val = mvpp2_read_relaxed(port->priv,  in mvpp2_aggr_desc_num_check()
2518 	u32 val;  in mvpp2_txq_alloc_reserved_desc()
2583 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,  in mvpp2_txq_desc_csum()
2586 	u32 command;  in mvpp2_txq_desc_csum()
2626 	u32 val;  in mvpp2_txq_sent_desc_proc()
2661 	u32	val, size, mtu;  in mvpp2_txp_max_tx_size_set()
2711 	u32 val;  in mvpp2_set_rxq_free_tresh()
2744 	u32 val;  in mvpp2_tx_pkts_coal_set()
2757 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)  in mvpp2_usec_to_cycles()
2766 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)  in mvpp2_cycles_to_usec()
2780 	u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);  in mvpp2_rx_time_coal_set()
2796 	u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);  in mvpp2_tx_time_coal_set()
2843 							u32 cause)  in mvpp2_get_rx_queue()
2851 							u32 cause)  in mvpp2_get_tx_queue()
2880 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,  in mvpp2_tx_done()
2911 	u32 txq_dma;  in mvpp2_aggr_txq_init()
2948 	u32 rxq_dma;  in mvpp2_rxq_init()
3041 		u32 status = mvpp2_rxdesc_status_get(port, rx_desc);  in mvpp2_rxq_drop_pkts()
3094 	u32 val;  in mvpp2_txq_init()
3229 	u32 val;  in mvpp2_txq_clean()
3277 	u32 val;  in mvpp2_cleanup_txqs()
3382 	u32 r0, r1, r2;  in mvpp2_isr_handle_ptp_queue()
3403 			u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;  in mvpp2_isr_handle_ptp_queue()
3415 	u32 val;  in mvpp2_isr_handle_ptp()
3457 	u32 val;  in mvpp2_isr_handle_xlg()
3470 	u32 val;  in mvpp2_isr_handle_gmac_internal()
3488 	u32 val;  in mvpp2_port_isr()
3553 	u32 status = mvpp2_rxdesc_status_get(port, rx_desc);  in mvpp2_rx_error()
3575 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status)  in mvpp2_rx_csum()
3608 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)  in mvpp2_skb_tx_csum()
3673 	u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |  in mvpp2_xdp_submit_frame()
3769 	       struct xdp_frame **frames, u32 flags)  in mvpp2_xdp_xmit()
3775 	u32 ret;  in mvpp2_xdp_xmit()
3818 	u32 ret, act;  in mvpp2_run_xdp()
3868 				    int pool, u32 rx_status)  in mvpp2_buff_hdr_pool_put()
3907 	u32 xdp_ret = 0;  in mvpp2_rx()
3924 		u32 rx_status, timestamp;  in mvpp2_rx()
4366 	u32 tx_cmd;  in mvpp2_tx()
4489 	u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;  in mvpp2_poll()
4567 	u32 ctrl3;  in mvpp22_mode_reconfigure()
4690 	u32 mac_addr_l, mac_addr_m, mac_addr_h;  in mvpp21_get_mac_address()
5176 	u32 gcr, int_mask;  in mvpp2_set_ts_config()
5594 				   struct ethtool_rxnfc *info, u32 *rules)  in mvpp2_ethtool_get_rxnfc()
5658 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)  in mvpp2_ethtool_get_rxfh_indir_size()
5665 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,  in mvpp2_ethtool_get_rxfh()
5683 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,  in mvpp2_ethtool_set_rxfh()
5704 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,  in mvpp2_ethtool_get_rxfh_context()
5705 					  u8 *key, u8 *hfunc, u32 rss_context)  in mvpp2_ethtool_get_rxfh_context()
5725 					  const u32 *indir, const u8 *key,  in mvpp2_ethtool_set_rxfh_context()
5726 					  const u8 hfunc, u32 *rss_context,  in mvpp2_ethtool_set_rxfh_context()
5906 	u32 val;  in mvpp2_rx_irqs_setup()
6184 	u32 val;  in mvpp2_xlg_pcs_get_state()
6236 	u32 val;  in mvpp2_gmac_pcs_get_state()
6273 	u32 mask, val, an, old_an, changed;  in mvpp2_gmac_pcs_config()
6327 	u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);  in mvpp2_gmac_pcs_an_restart()
6345 	u32 val;  in mvpp2_xlg_config()
6365 	u32 old_ctrl0, ctrl0;  in mvpp2_gmac_config()
6366 	u32 old_ctrl2, ctrl2;  in mvpp2_gmac_config()
6367 	u32 old_ctrl4, ctrl4;  in mvpp2_gmac_config()
6555 	u32 val;  in mvpp2_mac_link_up()
6635 	u32 val;  in mvpp2_mac_link_down()
6723 	u32 id;  in mvpp2_port_probe()
7081 	u32 win_enable;  in mvpp2_conf_mbus_windows()
7285 	u32 val, rdval, wrval;  in mvpp2_axi_init()
7342 	u32 val;  in mvpp2_init()
7524 		u32 addr_space_sz;  in mvpp2_probe()