Lines Matching full:c2
487 /* The default RxQ for this port is set in the C2 lookup */
491 * the C2 lookup.
495 /* CLS is always enabled, RSS is enabled/disabled in C2 lookup */
502 struct mvpp2_cls_c2_entry *c2)
505 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2->index);
508 if (c2->valid)
514 mvpp2_write(priv, MVPP22_CLS_C2_ACT, c2->act);
516 mvpp2_write(priv, MVPP22_CLS_C2_ATTR0, c2->attr[0]);
517 mvpp2_write(priv, MVPP22_CLS_C2_ATTR1, c2->attr[1]);
518 mvpp2_write(priv, MVPP22_CLS_C2_ATTR2, c2->attr[2]);
519 mvpp2_write(priv, MVPP22_CLS_C2_ATTR3, c2->attr[3]);
521 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]);
522 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]);
523 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]);
524 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]);
526 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]);
530 struct mvpp2_cls_c2_entry *c2)
535 c2->index = index;
537 c2->tcam[0] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA0);
538 c2->tcam[1] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA1);
539 c2->tcam[2] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA2);
540 c2->tcam[3] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA3);
541 c2->tcam[4] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA4);
543 c2->act = mvpp2_read(priv, MVPP22_CLS_C2_ACT);
545 c2->attr[0] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR0);
546 c2->attr[1] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR1);
547 c2->attr[2] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR2);
548 c2->attr[3] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR3);
551 c2->valid = !(val & MVPP22_CLS_C2_TCAM_INV_BIT);
601 /* RSS config C2 lookup */
869 struct mvpp2_cls_c2_entry c2;
872 memset(&c2, 0, sizeof(c2));
874 c2.index = MVPP22_CLS_C2_RSS_ENTRY(port->id);
877 c2.tcam[4] = MVPP22_CLS_C2_PORT_ID(pmap);
878 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_PORT_ID(pmap));
881 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK));
882 c2.tcam[4] |= MVPP22_CLS_C2_LU_TYPE(MVPP22_CLS_LU_TYPE_ALL);
885 c2.act = MVPP22_CLS_C2_ACT_RSS_EN(MVPP22_C2_UPD_LOCK);
888 c2.act |= MVPP22_CLS_C2_ACT_FWD(MVPP22_C2_FWD_SW_LOCK);
893 c2.act |= MVPP22_CLS_C2_ACT_QHIGH(MVPP22_C2_UPD) |
899 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) |
902 c2.valid = true;
904 mvpp2_cls_c2_write(port->priv, &c2);
912 struct mvpp2_cls_c2_entry c2;
936 /* Clear C2 TCAM engine table */
937 memset(&c2, 0, sizeof(c2));
938 c2.valid = false;
940 c2.index = index;
941 mvpp2_cls_c2_write(priv, &c2);
944 /* Disable the FIFO stages in C2 engine, which are only used in BIST
992 struct mvpp2_cls_c2_entry c2;
995 mvpp2_cls_c2_read(port->priv, MVPP22_CLS_C2_RSS_ENTRY(port->id), &c2);
1003 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) |
1006 c2.attr[2] |= MVPP22_CLS_C2_ATTR2_RSS_EN;
1008 mvpp2_cls_c2_write(port->priv, &c2);
1013 struct mvpp2_cls_c2_entry c2;
1016 mvpp2_cls_c2_read(port->priv, MVPP22_CLS_C2_RSS_ENTRY(port->id), &c2);
1022 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) |
1025 c2.attr[2] &= ~MVPP22_CLS_C2_ATTR2_RSS_EN;
1027 mvpp2_cls_c2_write(port->priv, &c2);
1057 struct mvpp2_cls_c2_entry c2;
1059 mvpp2_cls_c2_read(port->priv, entry, &c2);
1062 c2.tcam[4] &= ~(MVPP22_CLS_C2_PORT_ID(BIT(port->id)));
1064 mvpp2_cls_c2_write(port->priv, &c2);
1087 struct mvpp2_cls_c2_entry c2;
1094 memset(&c2, 0, sizeof(c2));
1099 c2.index = index;
1103 rule->c2_index = c2.index;
1105 c2.tcam[3] = (rule->c2_tcam & 0xffff) |
1107 c2.tcam[2] = ((rule->c2_tcam >> 16) & 0xffff) |
1109 c2.tcam[1] = ((rule->c2_tcam >> 32) & 0xffff) |
1111 c2.tcam[0] = ((rule->c2_tcam >> 48) & 0xffff) |
1115 c2.tcam[4] = MVPP22_CLS_C2_PORT_ID(pmap);
1116 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_PORT_ID(pmap));
1119 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK));
1120 c2.tcam[4] |= MVPP22_CLS_C2_LU_TYPE(rule->loc);
1123 c2.act = MVPP22_CLS_C2_ACT_COLOR(MVPP22_C2_COL_RED_LOCK);
1130 c2.act = MVPP22_CLS_C2_ACT_COLOR(MVPP22_C2_COL_NO_UPD_LOCK);
1134 c2.attr[2] |= MVPP22_CLS_C2_ATTR2_RSS_EN;
1140 c2.act = MVPP22_CLS_C2_ACT_RSS_EN(MVPP22_C2_UPD_LOCK);
1143 c2.act |= MVPP22_CLS_C2_ACT_FWD(MVPP22_C2_FWD_SW_LOCK);
1145 c2.act |= MVPP22_CLS_C2_ACT_QHIGH(MVPP22_C2_UPD_LOCK) |
1163 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) |
1167 c2.valid = true;
1169 mvpp2_cls_c2_write(port->priv, &c2);
1248 /* The order of insertion in C2 tcam must match the order in which
1331 /* For now, only use the C2 engine which has a HEK size limited to 64