34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port)	(0x00 + 4 * (port))  argument
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port)	(0x20 + 4 * (port))  argument
38 #define MVPP22_TX_FIFO_THRESH_REG(port)		(0x8840 + 4 * (port))  argument
39 #define MVPP22_TX_FIFO_SIZE_REG(port)		(0x8860 + 4 * (port))  argument
42 #define MVPP2_RX_CTRL_REG(port)			(0x140 + 4 * (port))  argument
61 #define MVPP2_MH_REG(port)			(0x5040 + 4 * (port))  argument
70 #define     MVPP2_PRS_PORT_LU_MASK(port)	(0xff << ((port) * 4))  argument
71 #define     MVPP2_PRS_PORT_LU_VAL(port, val)	((val) << ((port) * 4))  argument
72 #define MVPP2_PRS_INIT_OFFS_REG(port)		(0x1004 + ((port) & 4))  argument
73 #define     MVPP2_PRS_INIT_OFF_MASK(port)	(0x3f << (((port) % 4) * 8))  argument
74 #define     MVPP2_PRS_INIT_OFF_VAL(port, val)	((val) << (((port) % 4) * 8))  argument
75 #define MVPP2_PRS_MAX_LOOP_REG(port)		(0x100c + ((port) & 4))  argument
76 #define     MVPP2_PRS_MAX_LOOP_MASK(port)	(0xff << (((port) % 4) * 8))  argument
77 #define     MVPP2_PRS_MAX_LOOP_VAL(port, val)	((val) << (((port) % 4) * 8))  argument
103 #define     MVPP2_CLS_PORT_WAY_MASK(port)	(1 << (port))  argument
117 #define     MVPP2_CLS_FLOW_TBL0_PORT_ID(port)	((port) << 4)  argument
131 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port)	(0x1980 + ((port) * 4))  argument
134 #define MVPP2_CLS_SWFWD_P2HQ_REG(port)		(0x19b0 + ((port) * 4))  argument
136 #define     MVPP2_CLS_SWFWD_PCTRL_MASK(port)	(1 << (port))  argument
146 #define     MVPP22_CLS_C2_PORT_ID(port)		((port) << 8)  argument
258 #define MVPP2_ISR_TX_THRESHOLD_REG(port)	(0x5140 + 4 * (port))  argument
263 #define MVPP21_ISR_RXQ_GROUP_REG(port)		(0x5400 + 4 * (port))  argument
278 #define MVPP2_ISR_ENABLE_REG(port)		(0x5420 + 4 * (port))  argument
281 #define MVPP2_ISR_RX_TX_CAUSE_REG(port)		(0x5480 + 4 * (port))  argument
292 #define MVPP2_ISR_RX_TX_MASK_REG(port)		(0x54a0 + 4 * (port))  argument
298 #define MVPP2_ISR_RX_ERR_CAUSE_REG(port)	(0x5520 + 4 * (port))  argument
365 #define     MVPP22_CTRS_TX_CTR(port, txq)	((txq) | ((port) << 3) | BIT(7))  argument
410 #define     MVPP2_TX_PORT_FLUSH_MASK(port)	(1 << (port))  argument
590 #define MVPP22_GMAC_BASE(port)		(0x7000 + (port) * 0x1000 + 0xe00)  argument
599 #define MVPP22_MPCS_BASE(port)			(0x7000 + (port) * 0x1000)  argument
610 #define MVPP22_FCA_BASE(port)			(0x7600 + (port) * 0x1000)  argument
619 #define MVPP22_XPCS_BASE(port)			(0x7400 + (port) * 0x1000)  argument
626 #define MVPP22_PTP_BASE(port)			(0x7800 + (port * 0x1000))  argument
779 #define MVPP2_RX_FC_REG(port)		(0x150 + 4 * (port))  argument
1145 	struct mvpp2_port *port;  member
1484 	int port;  member
1565 static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)  in mvpp22_rx_hwtstamping()