434 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)  in wrlp()  function
454 	wrlp(mp, RXQ_COMMAND, 1 << rxq->index);  in rxq_enable()
462 	wrlp(mp, RXQ_COMMAND, mask << 8);  in rxq_disable()
474 	wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);  in txq_reset_hw_ptr()
480 	wrlp(mp, TXQ_COMMAND, 1 << txq->index);  in txq_enable()
488 	wrlp(mp, TXQ_COMMAND, mask << 8);  in txq_disable()
1153 		wrlp(mp, TX_BW_RATE, token_rate);  in tx_set_rate()
1154 		wrlp(mp, TX_BW_MTU, mtu);  in tx_set_rate()
1155 		wrlp(mp, TX_BW_BURST, bucket_size);  in tx_set_rate()
1158 		wrlp(mp, TX_BW_RATE_MOVED, token_rate);  in tx_set_rate()
1159 		wrlp(mp, TX_BW_MTU_MOVED, mtu);  in tx_set_rate()
1160 		wrlp(mp, TX_BW_BURST_MOVED, bucket_size);  in tx_set_rate()
1179 	wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);  in txq_set_rate()
1180 	wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);  in txq_set_rate()
1205 		wrlp(mp, off, val);  in txq_set_fixed_prio_mode()
1248 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);  in mv643xx_eth_adjust_link()
1393 	wrlp(mp, SDMA_CONFIG, val);  in set_rx_coal()
1419 	wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);  in set_tx_coal()
1691 	wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);  in mv643xx_eth_set_features()
1780 	wrlp(mp, MAC_ADDR_HIGH,  in uc_addr_set()
1782 	wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);  in uc_addr_set()
1841 	wrlp(mp, PORT_CONFIG, port_config);  in mv643xx_eth_program_unicast_filter()
2163 		wrlp(mp, INT_CAUSE, ~int_cause);  in mv643xx_eth_collect_events()
2171 		wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);  in mv643xx_eth_collect_events()
2188 	wrlp(mp, INT_MASK, 0);  in mv643xx_eth_irq()
2305 		wrlp(mp, INT_MASK, mp->int_mask);  in mv643xx_eth_poll()
2343 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);  in port_start()
2348 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);  in port_start()
2372 	wrlp(mp, PORT_CONFIG_EXT, 0x00000000);  in port_start()
2388 		wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);  in port_start()
2428 	wrlp(mp, INT_CAUSE, 0);  in mv643xx_eth_open()
2429 	wrlp(mp, INT_CAUSE_EXT, 0);  in mv643xx_eth_open()
2475 	wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);  in mv643xx_eth_open()
2476 	wrlp(mp, INT_MASK, mp->int_mask);  in mv643xx_eth_open()
2514 	wrlp(mp, PORT_SERIAL_CONTROL, data);  in port_reset()
2522 	wrlp(mp, INT_MASK_EXT, 0x00000000);  in mv643xx_eth_stop()
2523 	wrlp(mp, INT_MASK, 0x00000000);  in mv643xx_eth_stop()
2614 	wrlp(mp, INT_MASK, 0x00000000);  in mv643xx_eth_netpoll()
2619 	wrlp(mp, INT_MASK, mp->int_mask);  in mv643xx_eth_netpoll()
3055 		wrlp(mp, PORT_SERIAL_CONTROL, pscr);  in init_pscr()
3073 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);  in init_pscr()
3164 		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r);  in mv643xx_eth_probe()
3257 	wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);  in mv643xx_eth_probe()
3305 	wrlp(mp, INT_MASK, 0);  in mv643xx_eth_shutdown()