Lines Matching +full:0 +full:x0000c000

10 #define IXGBE_DPMCS_TDPAC       0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
11 #define IXGBE_DPMCS_TRM         0x00000010 /* Transmit Recycle Mode */
12 #define IXGBE_DPMCS_ARBDIS      0x00000040 /* DCB arbiter disable */
13 #define IXGBE_DPMCS_TSOEF       0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
15 #define IXGBE_RUPPBMR_MQA       0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP         0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores (RSS) enable */
25 #define IXGBE_TDTQ2TCCR_GSP     0x40000000
26 #define IXGBE_TDTQ2TCCR_LSP     0x80000000
30 #define IXGBE_TDPT2TCCR_GSP     0x40000000
31 #define IXGBE_TDPT2TCCR_LSP     0x80000000
33 #define IXGBE_PDPMCS_TPPAC      0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
34 #define IXGBE_PDPMCS_ARBDIS     0x00000040 /* Arbiter disable */
35 #define IXGBE_PDPMCS_TRM        0x00000100 /* Transmit Recycle Mode enable */
37 #define IXGBE_DTXCTL_ENDBUBD    0x00000004 /* Enable DBU buffer division */
39 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
40 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
41 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
42 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
44 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000