Lines Matching refs:u32
84 u32 pba, hwm; in igc_reset()
152 u32 ctrl_ext; in igc_release_hw_control()
174 u32 ctrl_ext; in igc_get_hw_control()
198 u32 xsk_frames = 0; in igc_clean_tx_ring()
323 u32 txdctl; in igc_disable_tx_ring_hw()
631 u32 srrctl = 0, rxdctl = 0; in igc_configure_rx_ring()
633 u32 buf_size; in igc_configure_rx_ring()
734 u32 txdctl = 0; in igc_configure_tx_ring()
781 u32 j, num_rx_queues; in igc_setup_mrqc()
782 u32 mrqc, rxcsum; in igc_setup_mrqc()
783 u32 rss_key[10]; in igc_setup_mrqc()
838 u32 rctl; in igc_setup_rctl()
885 u32 tctl; in igc_setup_tctl()
918 u32 ral, rah; in igc_set_mac_filter_hw()
1115 u32 cmd_type, olinfo_status; in igc_init_tx_empty_descriptor()
1150 u32 vlan_macip_lens, u32 type_tucmd, in igc_tx_ctxtdesc()
1151 u32 mss_l4len_idx) in igc_tx_ctxtdesc()
1181 u32 vlan_macip_lens = 0; in igc_tx_csum()
1182 u32 type_tucmd = 0; in igc_tx_csum()
1256 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
1257 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1259 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) in igc_tx_cmd_type()
1262 u32 cmd_type = IGC_ADVTXD_DTYP_DATA | in igc_tx_cmd_type()
1297 u32 tx_flags, unsigned int paylen) in igc_tx_olinfo_status()
1299 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT; in igc_tx_olinfo_status()
1321 u32 tx_flags = first->tx_flags; in igc_tx_map()
1326 u32 cmd_type; in igc_tx_map()
1457 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; in igc_tso()
1469 u32 paylen, l4_offset; in igc_tso()
1547 static bool igc_request_tx_tstamp(struct igc_adapter *adapter, struct sk_buff *skb, u32 *flags) in igc_request_tx_tstamp()
1576 u32 tx_flags = 0; in igc_xmit_frame_ring()
1644 u32 tstamp_flags; in igc_xmit_frame_ring()
1776 u32 rss_hash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); in igc_rx_hash()
1777 u32 rss_type = igc_rss_type(rx_desc); in igc_rx_hash()
1832 u32 ctrl; in igc_vlan_mode()
2088 u32 ntc = rx_ring->next_to_clean + 1; in igc_is_non_eop()
2355 u32 olinfo_status, len = xdpf->len, cmd_type; in igc_xdp_init_tx_descriptor()
2484 u32 act = bpf_prog_run_xdp(prog, xdp); in __igc_xdp_run_prog()
2898 u32 cmd_type, olinfo_status; in igc_xdp_xmit_zc()
2955 u32 xsk_frames = 0; in igc_clean_tx_irq()
3122 u32 ral, rah; in igc_find_mac_filter()
3149 u32 rah; in igc_get_avail_mac_filter_slot()
3244 u32 vlanpqf; in igc_add_vlan_prio_filter()
3271 u32 vlanpqf; in igc_del_vlan_prio_filter()
3290 u32 etqf = rd32(IGC_ETQF(i)); in igc_get_avail_etype_filter_slot()
3314 u32 etqf; in igc_add_etype_filter()
3346 u32 etqf = rd32(IGC_ETQF(i)); in igc_find_etype_filter()
3377 u32 *fhft) in igc_flex_filter_select()
3381 u32 fhftsl; in igc_flex_filter_select()
3423 u32 queuing; in igc_write_flex_filter_ll()
3424 u32 fhft; in igc_write_flex_filter_ll()
3425 u32 wufc; in igc_write_flex_filter_ll()
3466 u32 dw0 = in igc_write_flex_filter_ll()
3471 u32 dw1 = in igc_write_flex_filter_ll()
3476 u32 tmp; in igc_write_flex_filter_ll()
3493 u32 wufc_ext = rd32(IGC_WUFC_EXT); in igc_write_flex_filter_ll()
3537 u32 wufc, wufc_ext; in igc_find_avail_flex_filter_slot()
3559 u32 wufc, wufc_ext; in igc_flex_filter_in_use()
3653 u32 wufc; in igc_del_flex_filter()
3660 u32 wufc_ext = rd32(IGC_WUFC_EXT); in igc_del_flex_filter()
3759 u32 location) in igc_get_nfc_rule()
3876 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE; in igc_set_rx_mode()
3968 u32 ivar = array_rd32(IGC_IVAR0, index); in igc_write_ivar()
3971 ivar &= ~((u32)0xFF << offset); in igc_write_ivar()
4026 u32 tmp; in igc_configure_msix()
4068 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA; in igc_irq_enable()
4069 u32 regval = rd32(IGC_EIAC); in igc_irq_enable()
4091 u32 regval = rd32(IGC_EIAM); in igc_irq_disable()
4116 const u32 max_rss_queues) in igc_set_flag_queue_pairs()
4135 u32 max_rss_queues; in igc_init_queue_configuration()
4138 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); in igc_init_queue_configuration()
4282 u32 new_itr = q_vector->itr_val; in igc_set_itr()
4468 avg_wire_size = max_t(u32, avg_wire_size, in igc_update_ring_itr()
4894 u32 mpc; in igc_update_stats()
4911 u32 rqdpc = rd32(IGC_RQDPC(i)); in igc_update_stats()
5057 u32 tctl, rctl; in igc_down()
5304 u32 tsauxc, sec, nsec, tsicr; in igc_tsync_interrupt()
5326 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec); in igc_tsync_interrupt()
5339 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec); in igc_tsync_interrupt()
5375 u32 icr = rd32(IGC_ICR); in igc_msix_other()
5403 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK; in igc_write_itr()
5569 u32 link; in igc_watchdog_task()
5586 u32 ctrl; in igc_watchdog_task()
5710 u32 eics = 0; in igc_watchdog_task()
5743 u32 icr = rd32(IGC_ICR); in igc_intr_msi()
5782 u32 icr = rd32(IGC_ICR); in igc_intr()
6205 u32 start_time = 0, end_time = 0; in igc_save_qbv_schedule()
6477 struct xdp_frame **frames, u32 flags) in igc_xdp_xmit()
6522 u32 eics = 0; in igc_trigger_rxtxq_interrupt()
6528 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags) in igc_xsk_wakeup()
6575 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) in igc_read_pci_cfg()
6582 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) in igc_write_pci_cfg()
6589 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) in igc_read_pcie_cap_reg()
6601 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) in igc_write_pcie_cap_reg()
6613 u32 igc_rd32(struct igc_hw *hw, u32 reg) in igc_rd32()
6617 u32 value = 0; in igc_rd32()
6658 static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash, in igc_xdp_rx_hash()
7023 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol; in __igc_shutdown()
7025 u32 ctrl, rctl, status; in __igc_shutdown()
7098 u32 wupl; in igc_deliver_wake_packet()
7129 u32 err, val; in igc_resume()
7373 u32 rxdctl; in igc_disable_rx_ring_hw()