1 // SPDX-License-Identifier: GPL-2.0
13  * igc_reset_hw_base - Reset hardware
22 	u32 ctrl;  in igc_reset_hw_base()  local
24 	/* Prevent the PCI-E bus from sticking if there is no TLP connection  in igc_reset_hw_base()
29 		hw_dbg("PCI-E Master disable polling has failed\n");  in igc_reset_hw_base()
40 	ctrl = rd32(IGC_CTRL);  in igc_reset_hw_base()
43 	wr32(IGC_CTRL, ctrl | IGC_CTRL_RST);  in igc_reset_hw_base()
62  * igc_init_nvm_params_base - Init NVM func ptrs.
67 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_init_nvm_params_base()
73 		return -ENXIO;  in igc_init_nvm_params_base()
77 	/* Added to a constant, "size" becomes the left-shift value  in igc_init_nvm_params_base()
88 	nvm->type = igc_nvm_eeprom_spi;  in igc_init_nvm_params_base()
89 	nvm->word_size = BIT(size);  in igc_init_nvm_params_base()
90 	nvm->opcode_bits = 8;  in igc_init_nvm_params_base()
91 	nvm->delay_usec = 1;  in igc_init_nvm_params_base()
93 	nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;  in igc_init_nvm_params_base()
94 	nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?  in igc_init_nvm_params_base()
97 	if (nvm->word_size == BIT(15))  in igc_init_nvm_params_base()
98 		nvm->page_size = 128;  in igc_init_nvm_params_base()
104  * igc_setup_copper_link_base - Configure copper link settings
107  * Configures the link for auto-neg or forced speed and duplex.  Then we check
114 	u32 ctrl;  in igc_setup_copper_link_base()  local
116 	ctrl = rd32(IGC_CTRL);  in igc_setup_copper_link_base()
117 	ctrl |= IGC_CTRL_SLU;  in igc_setup_copper_link_base()
118 	ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);  in igc_setup_copper_link_base()
119 	wr32(IGC_CTRL, ctrl);  in igc_setup_copper_link_base()
127  * igc_init_mac_params_base - Init MAC func ptrs.
132 	struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base;  in igc_init_mac_params_base()
133 	struct igc_mac_info *mac = &hw->mac;  in igc_init_mac_params_base()
136 	mac->mta_reg_count = 128;  in igc_init_mac_params_base()
137 	mac->rar_entry_count = IGC_RAR_ENTRIES;  in igc_init_mac_params_base()
140 	mac->ops.reset_hw = igc_reset_hw_base;  in igc_init_mac_params_base()
142 	mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;  in igc_init_mac_params_base()
143 	mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;  in igc_init_mac_params_base()
146 	if (mac->type == igc_i225)  in igc_init_mac_params_base()
147 		dev_spec->clear_semaphore_once = true;  in igc_init_mac_params_base()
150 	mac->ops.setup_physical_interface = igc_setup_copper_link_base;  in igc_init_mac_params_base()
156  * igc_init_phy_params_base - Init PHY func ptrs.
161 	struct igc_phy_info *phy = &hw->phy;  in igc_init_phy_params_base()
164 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;  in igc_init_phy_params_base()
165 	phy->reset_delay_us	= 100;  in igc_init_phy_params_base()
168 	hw->bus.func = FIELD_GET(IGC_STATUS_FUNC_MASK, rd32(IGC_STATUS));  in igc_init_phy_params_base()
175 	ret_val = hw->phy.ops.reset(hw);  in igc_init_phy_params_base()
193 	struct igc_mac_info *mac = &hw->mac;  in igc_get_invariants_base()
196 	switch (hw->device_id) {  in igc_get_invariants_base()
213 		mac->type = igc_i225;  in igc_get_invariants_base()
216 		return -IGC_ERR_MAC_INIT;  in igc_get_invariants_base()
219 	hw->phy.media_type = igc_media_type_copper;  in igc_get_invariants_base()
230 	switch (hw->mac.type) {  in igc_get_invariants_base()
248  * igc_acquire_phy_base - Acquire rights to access PHY
258 	return hw->mac.ops.acquire_swfw_sync(hw, mask);  in igc_acquire_phy_base()
262  * igc_release_phy_base - Release rights to access PHY
272 	hw->mac.ops.release_swfw_sync(hw, mask);  in igc_release_phy_base()
276  * igc_init_hw_base - Initialize hardware
283 	struct igc_mac_info *mac = &hw->mac;  in igc_init_hw_base()
284 	u16 i, rar_count = mac->rar_entry_count;  in igc_init_hw_base()
292 	for (i = 0; i < mac->mta_reg_count; i++)  in igc_init_hw_base()
297 	for (i = 0; i < mac->uta_reg_count; i++)  in igc_init_hw_base()
314  * igc_power_down_phy_copper_base - Remove link during PHY power down
328  * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable
331  * After Rx enable, if manageability is enabled then there is likely some
333  * function clears the fifos and flushes any packets that came in as rx was
349 	/* Disable all Rx queues */  in igc_rx_fifo_flush_base()
386 	/* Enable Rx queues that were previously enabled and restore our  in igc_rx_fifo_flush_base()
405 	switch (hw->device_id) {  in igc_is_device_id_i225()
421 	switch (hw->device_id) {  in igc_is_device_id_i226()