intel/igc/igc.h

93 struct igc_ring {  struct
94 	struct igc_q_vector *q_vector;  /* backlink to q_vector */
95 	struct net_device *netdev;      /* back pointer to net_device */
96 	struct device *dev;             /* device for dma mapping */
97 	union {                         /* array of buffer info structs */
101 	void *desc;                     /* descriptor ring memory */
102 	unsigned long flags;            /* ring specific flags */
103 	void __iomem *tail;             /* pointer to ring tail register */
104 	dma_addr_t dma;                 /* phys address of the ring */
105 	unsigned int size;              /* length of desc. ring in bytes */
107 	u16 count;                      /* number of desc. in the ring */
108 	u8 queue_index;                 /* logical index of the ring*/
109 	u8 reg_idx;                     /* physical index of the ring */
110 	bool launchtime_enable;         /* true if LaunchTime is enabled */
111 	ktime_t last_tx_cycle;          /* end of the cycle with a launchtime transmission */
112 	ktime_t last_ff_cycle;          /* Last cycle with an active first flag */
114 	u32 start_time;
115 	u32 end_time;
116 	u32 max_sdu;
117 	bool oper_gate_closed;		/* Operating gate. True if the TX Queue is closed */
118 	bool admin_gate_closed;		/* Future gate. True if the TX Queue will be closed */
121 	bool cbs_enable;                /* indicates if CBS is enabled */
122 	s32 idleslope;                  /* idleSlope in kbps */
123 	s32 sendslope;                  /* sendSlope in kbps */
124 	s32 hicredit;                   /* hiCredit in bytes */
125 	s32 locredit;                   /* loCredit in bytes */
128 	u16 next_to_clean;
129 	u16 next_to_use;
130 	u16 next_to_alloc;
132 	union {
169 	struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];  argument