Lines Matching +full:0 +full:x4fc
128 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
203 #define ICE_PTP_CLOCK_INDEX_0 0x00
204 #define ICE_PTP_CLOCK_INDEX_1 0x01
211 #define GLTSYN_CMD_INIT_TIME BIT(0)
213 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
219 #define PHY_CMD_INIT_TIME BIT(0)
221 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
222 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
223 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
225 #define TS_CMD_MASK_E810 0xFF
226 #define TS_CMD_MASK 0xF
227 #define SYNC_EXEC_CMD 0x3
230 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
231 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
232 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
233 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
236 #define Q_0_BASE 0x94000
237 #define Q_1_BASE 0x114000
240 #define Q_REG_TS_CTRL 0x618
241 #define Q_REG_TS_CTRL_S 0
242 #define Q_REG_TS_CTRL_M BIT(0)
245 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
246 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
249 #define Q_REG_FIFO23_STATUS 0xCF8
250 #define Q_REG_FIFO01_STATUS 0xCFC
251 #define Q_REG_FIFO02_S 0
252 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
254 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
257 #define Q_REG_TX_MEM_GBL_CFG 0xC08
258 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
259 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
261 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
263 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
268 #define Q_REG_TX_MEMORY_BANK_START 0xA00
271 #define P_0_BASE 0x80000
272 #define P_4_BASE 0x106000
275 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
276 #define P_REG_RX_TIMER_INC_PRE_U 0x470
277 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
278 #define P_REG_TX_TIMER_INC_PRE_U 0x450
281 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
282 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
283 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
284 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
287 #define P_REG_RX_CAPTURE_L 0x4D8
288 #define P_REG_RX_CAPTURE_U 0x4DC
289 #define P_REG_TX_CAPTURE_L 0x4B4
290 #define P_REG_TX_CAPTURE_U 0x4B8
293 #define P_REG_TIMETUS_L 0x410
294 #define P_REG_TIMETUS_U 0x414
296 #define P_REG_40B_LOW_M 0xFF
300 #define P_REG_WL 0x40C
302 #define PTP_VERNIER_WL 0x111ed
305 #define P_REG_PS 0x408
306 #define P_REG_PS_START_S 0
307 #define P_REG_PS_START_M BIT(0)
318 #define P_REG_TX_OV_STATUS 0x4D4
319 #define P_REG_TX_OV_STATUS_OV_S 0
320 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
321 #define P_REG_RX_OV_STATUS 0x4F8
322 #define P_REG_RX_OV_STATUS_OV_S 0
323 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
326 #define P_REG_TX_OR 0x45C
327 #define P_REG_RX_OR 0x47C
330 #define P_REG_TOTAL_RX_OFFSET_L 0x460
331 #define P_REG_TOTAL_RX_OFFSET_U 0x464
332 #define P_REG_TOTAL_TX_OFFSET_L 0x440
333 #define P_REG_TOTAL_TX_OFFSET_U 0x444
336 #define P_REG_UIX66_10G_40G_L 0x480
337 #define P_REG_UIX66_10G_40G_U 0x484
338 #define P_REG_UIX66_25G_100G_L 0x488
339 #define P_REG_UIX66_25G_100G_U 0x48C
340 #define P_REG_DESK_PAR_RX_TUS_L 0x490
341 #define P_REG_DESK_PAR_RX_TUS_U 0x494
342 #define P_REG_DESK_PAR_TX_TUS_L 0x498
343 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
344 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
345 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
346 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
347 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
348 #define P_REG_PAR_RX_TUS_L 0x420
349 #define P_REG_PAR_RX_TUS_U 0x424
350 #define P_REG_PAR_TX_TUS_L 0x428
351 #define P_REG_PAR_TX_TUS_U 0x42C
352 #define P_REG_PCS_RX_TUS_L 0x430
353 #define P_REG_PCS_RX_TUS_U 0x434
354 #define P_REG_PCS_TX_TUS_L 0x438
355 #define P_REG_PCS_TX_TUS_U 0x43C
356 #define P_REG_PAR_RX_TIME_L 0x4F0
357 #define P_REG_PAR_RX_TIME_U 0x4F4
358 #define P_REG_PAR_TX_TIME_L 0x4CC
359 #define P_REG_PAR_TX_TIME_U 0x4D0
360 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
361 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
362 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
363 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
364 #define P_REG_LINK_SPEED 0x4FC
365 #define P_REG_LINK_SPEED_SERDES_S 0
366 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
368 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
374 #define P_REG_PMD_ALIGNMENT 0x0FC
375 #define P_REG_RX_80_TO_160_CNT 0x6FC
376 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
377 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
378 #define P_REG_RX_40_TO_160_CNT 0x8FC
379 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
380 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
383 #define P_REG_RX_OV_FS 0x4F8
385 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
388 #define P_REG_TX_TMR_CMD 0x448
389 #define P_REG_RX_TMR_CMD 0x468
392 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
395 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
396 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
399 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
400 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
403 #define ETH_GLTSYN_CMD 0x03000344
406 #define INCVAL_HIGH_M 0xFF
409 #define TS_VALID BIT(0)
410 #define TS_LOW_M 0xFFFFFFFF
411 #define TS_HIGH_M 0xFF
414 #define TS_PHY_LOW_M 0xFF
415 #define TS_PHY_HIGH_M 0xFFFFFFFF
433 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
436 #define LOW_TX_MEMORY_BANK_START 0x03090000
437 #define HIGH_TX_MEMORY_BANK_START 0x03090004
459 #define ICE_PCA9575_P0_IN 0x0