21 #define HINIC_CSR_DMA_ATTR_ADDR(idx)                    \  argument
22 	(HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
26 #define HINIC_CSR_PPF_ELECTION_ADDR(idx)                \  argument
27 	(HINIC_ELECTION_BASE +  (idx) * HINIC_PPF_ELECTION_STRIDE)
34 #define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)       \  argument
35 	(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
37 #define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)       \  argument
38 	(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
40 #define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)           \  argument
41 	(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
43 #define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)           \  argument
44 	(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
46 #define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)     \  argument
47 	(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
49 #define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)          \  argument
50 	(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
52 #define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)            \  argument
53 	(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
55 #define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)           \  argument
56 	(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
58 #define HINIC_CSR_API_CMD_STATUS_ADDR(idx)              \  argument
59 	(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
67 #define HINIC_CSR_MSIX_CTRL_ADDR(idx)                   \  argument
68 	(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
70 #define HINIC_CSR_MSIX_CNT_ADDR(idx)                    \  argument
71 	(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
115 #define HINIC_CSR_AEQ_CTRL_0_ADDR(idx)                  \  argument
116 	(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
118 #define HINIC_CSR_AEQ_CTRL_1_ADDR(idx)                  \  argument
119 	(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
121 #define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx)                \  argument
122 	(HINIC_AEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
124 #define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx)                \  argument
125 	(HINIC_AEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
127 #define HINIC_CSR_CEQ_CTRL_0_ADDR(idx)                  \  argument
128 	(HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
130 #define HINIC_CSR_CEQ_CTRL_1_ADDR(idx)                  \  argument
131 	(HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
133 #define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx)                \  argument
134 	(HINIC_CEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
136 #define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx)                \  argument
137 	(HINIC_CEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)