Lines Matching refs:u32
23 u32 fec_reserved0;
24 u32 fec_ievent; /* Interrupt event reg */
25 u32 fec_imask; /* Interrupt mask reg */
26 u32 fec_reserved1;
27 u32 fec_r_des_active; /* Receive descriptor reg */
28 u32 fec_x_des_active; /* Transmit descriptor reg */
29 u32 fec_reserved2[3];
30 u32 fec_ecntrl; /* Ethernet control reg */
31 u32 fec_reserved3[6];
32 u32 fec_mii_data; /* MII manage frame reg */
33 u32 fec_mii_speed; /* MII speed control reg */
34 u32 fec_reserved4[7];
35 u32 fec_mib_ctrlstat; /* MIB control/status reg */
36 u32 fec_reserved5[7];
37 u32 fec_r_cntrl; /* Receive control reg */
38 u32 fec_reserved6[15];
39 u32 fec_x_cntrl; /* Transmit Control reg */
40 u32 fec_reserved7[7];
41 u32 fec_addr_low; /* Low 32bits MAC address */
42 u32 fec_addr_high; /* High 16bits MAC address */
43 u32 fec_opd; /* Opcode + Pause duration */
44 u32 fec_reserved8[10];
45 u32 fec_hash_table_high; /* High 32bits hash table */
46 u32 fec_hash_table_low; /* Low 32bits hash table */
47 u32 fec_grp_hash_table_high; /* High 32bits hash table */
48 u32 fec_grp_hash_table_low; /* Low 32bits hash table */
49 u32 fec_reserved9[7];
50 u32 fec_x_wmrk; /* FIFO transmit water mark */
51 u32 fec_reserved10;
52 u32 fec_r_bound; /* FIFO receive bound reg */
53 u32 fec_r_fstart; /* FIFO receive start reg */
54 u32 fec_reserved11[11];
55 u32 fec_r_des_start; /* Receive descriptor ring */
56 u32 fec_x_des_start; /* Transmit descriptor ring */
57 u32 fec_r_buff_size; /* Maximum receive buff size */
58 u32 fec_reserved12[26];
59 u32 fec_dma_control; /* DMA Endian and other ctrl */
65 u32 mii_speed;
88 u32 (*get_int_events)(struct net_device *dev);
89 void (*clear_int_events)(struct net_device *dev, u32 int_events);
90 void (*ev_error)(struct net_device *dev, u32 int_events);
121 u32 cp_command; /* CPM page/sblock/mcn */
123 u32 dpram_offset;
158 u32 msg_enable;
166 u32 ev_napi; /* mask of NAPI events */
167 u32 ev; /* event mask */
168 u32 ev_err; /* error event mask */
177 u32 hthi, htlo; /* state for multicast */
186 u32 gaddrh, gaddrl; /* group address */
193 u32 hthi, htlo; /* state for multicast */