Lines Matching defs:fman_port_rx_bmi_regs
174 struct fman_port_rx_bmi_regs { struct
175 u32 fmbm_rcfg; /* Rx Configuration */
176 u32 fmbm_rst; /* Rx Status */
177 u32 fmbm_rda; /* Rx DMA attributes */
178 u32 fmbm_rfp; /* Rx FIFO Parameters */
179 u32 fmbm_rfed; /* Rx Frame End Data */
180 u32 fmbm_ricp; /* Rx Internal Context Parameters */
181 u32 fmbm_rim; /* Rx Internal Buffer Margins */
182 u32 fmbm_rebm; /* Rx External Buffer Margins */
183 u32 fmbm_rfne; /* Rx Frame Next Engine */
184 u32 fmbm_rfca; /* Rx Frame Command Attributes. */
185 u32 fmbm_rfpne; /* Rx Frame Parser Next Engine */
186 u32 fmbm_rpso; /* Rx Parse Start Offset */
187 u32 fmbm_rpp; /* Rx Policer Profile */
188 u32 fmbm_rccb; /* Rx Coarse Classification Base */
189 u32 fmbm_reth; /* Rx Excessive Threshold */
190 u32 reserved003c[1]; /* (0x03C 0x03F) */
191 u32 fmbm_rprai[PORT_PRS_RESULT_WORDS_NUM];
193 u32 fmbm_rfqid; /* Rx Frame Queue ID */
194 u32 fmbm_refqid; /* Rx Error Frame Queue ID */
195 u32 fmbm_rfsdm; /* Rx Frame Status Discard Mask */
196 u32 fmbm_rfsem; /* Rx Frame Status Error Mask */
197 u32 fmbm_rfene; /* Rx Frame Enqueue Next Engine */
198 u32 reserved0074[0x2]; /* (0x074-0x07C) */
199 u32 fmbm_rcmne; /* Rx Frame Continuous Mode Next Engine */
200 u32 reserved0080[0x20]; /* (0x080 0x0FF) */
201 u32 fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
203 u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; /* Allocate Counter- */
204 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */
205 u32 fmbm_rcgm[PORT_CG_MAP_NUM]; /* Congestion Group Map */
206 u32 fmbm_mpd; /* BM Pool Depletion */
207 u32 reserved0184[0x1F]; /* (0x184 0x1FF) */
208 u32 fmbm_rstc; /* Rx Statistics Counters */
209 u32 fmbm_rfrc; /* Rx Frame Counter */
210 u32 fmbm_rfbc; /* Rx Bad Frames Counter */
211 u32 fmbm_rlfc; /* Rx Large Frames Counter */
212 u32 fmbm_rffc; /* Rx Filter Frames Counter */
213 u32 fmbm_rfdc; /* Rx Frame Discard Counter */
214 u32 fmbm_rfldec; /* Rx Frames List DMA Error Counter */
215 u32 fmbm_rodc; /* Rx Out of Buffers Discard nntr */
216 u32 fmbm_rbdc; /* Rx Buffers Deallocate Counter */
217 u32 fmbm_rpec; /* RX Prepare to enqueue Counte */
218 u32 reserved0224[0x16]; /* (0x224 0x27F) */
219 u32 fmbm_rpc; /* Rx Performance Counters */
220 u32 fmbm_rpcp; /* Rx Performance Count Parameters */
221 u32 fmbm_rccn; /* Rx Cycle Counter */
222 u32 fmbm_rtuc; /* Rx Tasks Utilization Counter */
223 u32 fmbm_rrquc; /* Rx Receive Queue Utilization cntr */
224 u32 fmbm_rduc; /* Rx DMA Utilization Counter */
225 u32 fmbm_rfuc; /* Rx FIFO Utilization Counter */
226 u32 fmbm_rpac; /* Rx Pause Activation Counter */
227 u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */
228 u32 fmbm_rdcfg[0x3]; /* Rx Debug Configuration */
229 u32 fmbm_rgpr; /* Rx General Purpose Register */
230 u32 reserved0310[0x3a];