Lines Matching defs:dtsec_regs
155 struct dtsec_regs { struct
157 u32 tsec_id; /* 0x000 ETSEC_ID register */
158 u32 tsec_id2; /* 0x004 ETSEC_ID2 register */
159 u32 ievent; /* 0x008 Interrupt event register */
160 u32 imask; /* 0x00C Interrupt mask register */
161 u32 reserved0010[1];
162 u32 ecntrl; /* 0x014 E control register */
163 u32 ptv; /* 0x018 Pause time value register */
164 u32 tbipa; /* 0x01C TBI PHY address register */
165 u32 tmr_ctrl; /* 0x020 Time-stamp Control register */
166 u32 tmr_pevent; /* 0x024 Time-stamp event register */
167 u32 tmr_pemask; /* 0x028 Timer event mask register */
168 u32 reserved002c[5];
169 u32 tctrl; /* 0x040 Transmit control register */
170 u32 reserved0044[3];
171 u32 rctrl; /* 0x050 Receive control register */
172 u32 reserved0054[11];
173 u32 igaddr[8]; /* 0x080-0x09C Individual/group address */
174 u32 gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
175 u32 reserved00c0[16];
176 u32 maccfg1; /* 0x100 MAC configuration #1 */
177 u32 maccfg2; /* 0x104 MAC configuration #2 */
178 u32 ipgifg; /* 0x108 IPG/IFG */
179 u32 hafdup; /* 0x10C Half-duplex */
180 u32 maxfrm; /* 0x110 Maximum frame */
181 u32 reserved0114[10];
182 u32 ifstat; /* 0x13C Interface status */
183 u32 macstnaddr1; /* 0x140 Station Address,part 1 */
184 u32 macstnaddr2; /* 0x144 Station Address,part 2 */
185 struct {
188 } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */
189 u32 reserved01c0[16];
190 u32 tr64; /* 0x200 Tx and Rx 64 byte frame counter */
191 u32 tr127; /* 0x204 Tx and Rx 65 to 127 byte frame counter */
192 u32 tr255; /* 0x208 Tx and Rx 128 to 255 byte frame counter */
193 u32 tr511; /* 0x20C Tx and Rx 256 to 511 byte frame counter */
194 u32 tr1k; /* 0x210 Tx and Rx 512 to 1023 byte frame counter */
195 u32 trmax; /* 0x214 Tx and Rx 1024 to 1518 byte frame counter */
196 u32 trmgv;
198 u32 rbyt; /* 0x21C receive byte counter */
199 u32 rpkt; /* 0x220 receive packet counter */
200 u32 rfcs; /* 0x224 receive FCS error counter */
201 u32 rmca; /* 0x228 RMCA Rx multicast packet counter */
202 u32 rbca; /* 0x22C Rx broadcast packet counter */
203 u32 rxcf; /* 0x230 Rx control frame packet counter */
204 u32 rxpf; /* 0x234 Rx pause frame packet counter */
205 u32 rxuo; /* 0x238 Rx unknown OP code counter */
206 u32 raln; /* 0x23C Rx alignment error counter */
207 u32 rflr; /* 0x240 Rx frame length error counter */
208 u32 rcde; /* 0x244 Rx code error counter */
209 u32 rcse; /* 0x248 Rx carrier sense error counter */
210 u32 rund; /* 0x24C Rx undersize packet counter */
211 u32 rovr; /* 0x250 Rx oversize packet counter */
212 u32 rfrg; /* 0x254 Rx fragments counter */
213 u32 rjbr; /* 0x258 Rx jabber counter */
214 u32 rdrp; /* 0x25C Rx drop */
215 u32 tbyt; /* 0x260 Tx byte counter */
216 u32 tpkt; /* 0x264 Tx packet counter */
217 u32 tmca; /* 0x268 Tx multicast packet counter */
218 u32 tbca; /* 0x26C Tx broadcast packet counter */
219 u32 txpf; /* 0x270 Tx pause control frame counter */
220 u32 tdfr; /* 0x274 Tx deferral packet counter */
221 u32 tedf; /* 0x278 Tx excessive deferral packet counter */
222 u32 tscl; /* 0x27C Tx single collision packet counter */
223 u32 tmcl; /* 0x280 Tx multiple collision packet counter */
224 u32 tlcl; /* 0x284 Tx late collision packet counter */
225 u32 txcl; /* 0x288 Tx excessive collision packet counter */
226 u32 tncl; /* 0x28C Tx total collision counter */
227 u32 reserved0290[1];
228 u32 tdrp; /* 0x294 Tx drop frame counter */
229 u32 tjbr; /* 0x298 Tx jabber frame counter */
230 u32 tfcs; /* 0x29C Tx FCS error counter */
231 u32 txcf; /* 0x2A0 Tx control frame counter */
232 u32 tovr; /* 0x2A4 Tx oversize frame counter */
233 u32 tund; /* 0x2A8 Tx undersize frame counter */
234 u32 tfrg; /* 0x2AC Tx fragments frame counter */
235 u32 car1; /* 0x2B0 carry register one register* */
236 u32 car2; /* 0x2B4 carry register two register* */
237 u32 cam1; /* 0x2B8 carry register one mask register */
238 u32 cam2; /* 0x2BC carry register two mask register */
239 u32 reserved02c0[848];