Lines Matching +full:scaled +full:- +full:output +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
93 * fec_ptp_read - read raw cycle counter (to be used by time counter)
106 tempval = readl(fep->hwp + FEC_ATIME_CTRL);
108 writel(tempval, fep->hwp + FEC_ATIME_CTRL);
110 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE)
113 return readl(fep->hwp + FEC_ATIME);
119 * @enable: enable the channel pps output
130 spin_lock_irqsave(&fep->tmreg_lock, flags);
132 if (fep->pps_enable == enable) {
133 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
138 /* clear capture or output compare interrupt status if have.
140 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
146 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
149 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
150 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
154 timecounter_read(&fep->tc);
159 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
162 tempval = fec_ptp_read(&fep->cc);
164 ns = timecounter_cyc2time(&fep->tc, tempval);
170 val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
174 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
179 * of next second. The current setting is 31-bit timer and wrap
185 /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
186 * ptp counter, which maybe cause 32-bit wrap. Since the
187 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
189 * is bigger than fep->cc.mask would be a error.
191 val &= fep->cc.mask;
192 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
195 fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
198 val = readl(fep->hwp + FEC_ATIME_CTRL);
200 writel(val, fep->hwp + FEC_ATIME_CTRL);
203 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
208 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
213 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
214 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
216 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
219 fep->pps_enable = enable;
220 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
231 spin_lock_irqsave(&fep->tmreg_lock, flags);
234 timecounter_read(&fep->tc);
237 ptp_hc = fec_ptp_read(&fep->cc);
240 curr_time = timecounter_cyc2time(&fep->tc, ptp_hc);
246 if (fep->perout_stime < curr_time + 100 * NSEC_PER_MSEC) {
247 dev_err(&fep->pdev->dev, "Current time is too close to the start time!\n");
248 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
249 return -1;
252 compare_val = fep->perout_stime - curr_time + ptp_hc;
253 compare_val &= fep->cc.mask;
255 writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel));
256 fep->next_counter = (compare_val + fep->reload_period) & fep->cc.mask;
259 temp_val = readl(fep->hwp + FEC_ATIME_CTRL);
261 writel(temp_val, fep->hwp + FEC_ATIME_CTRL);
264 temp_val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
269 writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel));
274 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
275 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
276 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
292 * fec_ptp_start_cyclecounter - create the cycle counter from hw
305 inc = 1000000000 / fep->cycle_speed;
308 spin_lock_irqsave(&fep->tmreg_lock, flags);
311 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
313 /* use 31-bit timer counter */
314 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
317 fep->hwp + FEC_ATIME_CTRL);
319 memset(&fep->cc, 0, sizeof(fep->cc));
320 fep->cc.read = fec_ptp_read;
321 fep->cc.mask = CLOCKSOURCE_MASK(31);
322 fep->cc.shift = 31;
323 fep->cc.mult = FEC_CC_MULT;
326 timecounter_init(&fep->tc, &fep->cc, 0);
328 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
332 * fec_ptp_adjfine - adjust ptp cycle frequency
334 * @scaled_ppm: scaled parts per million adjustment from base
339 * Scaled parts per million is ppm with a 16-bit binary fractional field.
361 ppb = -ppb;
366 * Try to find the corr_inc between 1 to fep->ptp_inc to
370 rhs = (u64)ppb * (u64)fep->ptp_inc;
371 for (i = 1; i <= fep->ptp_inc; i++) {
379 /* Not found? Set it to high value - double speed
382 if (i > fep->ptp_inc) {
383 corr_inc = fep->ptp_inc;
388 corr_ns = fep->ptp_inc - corr_inc;
390 corr_ns = fep->ptp_inc + corr_inc;
392 spin_lock_irqsave(&fep->tmreg_lock, flags);
394 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
396 writel(tmp, fep->hwp + FEC_ATIME_INC);
397 corr_period = corr_period > 1 ? corr_period - 1 : corr_period;
398 writel(corr_period, fep->hwp + FEC_ATIME_CORR);
400 timecounter_read(&fep->tc);
402 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
420 spin_lock_irqsave(&fep->tmreg_lock, flags);
421 timecounter_adjtime(&fep->tc, delta);
422 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
442 mutex_lock(&fep->ptp_clk_mutex);
444 if (!fep->ptp_clk_on) {
445 mutex_unlock(&fep->ptp_clk_mutex);
446 return -EINVAL;
448 spin_lock_irqsave(&fep->tmreg_lock, flags);
449 ns = timecounter_read(&fep->tc);
450 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
451 mutex_unlock(&fep->ptp_clk_mutex);
476 mutex_lock(&fep->ptp_clk_mutex);
478 if (!fep->ptp_clk_on) {
479 mutex_unlock(&fep->ptp_clk_mutex);
480 return -EINVAL;
487 counter = ns & fep->cc.mask;
489 spin_lock_irqsave(&fep->tmreg_lock, flags);
490 writel(counter, fep->hwp + FEC_ATIME);
491 timecounter_init(&fep->tc, &fep->cc, ns);
492 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
493 mutex_unlock(&fep->ptp_clk_mutex);
501 spin_lock_irqsave(&fep->tmreg_lock, flags);
502 writel(0, fep->hwp + FEC_TCSR(channel));
503 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
526 if (rq->type == PTP_CLK_REQ_PPS) {
527 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
532 } else if (rq->type == PTP_CLK_REQ_PEROUT) {
534 if (rq->perout.flags)
535 return -EOPNOTSUPP;
537 if (rq->perout.index != fep->pps_channel)
538 return -EOPNOTSUPP;
540 period.tv_sec = rq->perout.period.sec;
541 period.tv_nsec = rq->perout.period.nsec;
548 dev_err(&fep->pdev->dev, "The period must equal to or less than 4s!\n");
549 return -EOPNOTSUPP;
552 fep->reload_period = div_u64(period_ns, 2);
553 if (on && fep->reload_period) {
555 start_time.tv_sec = rq->perout.start.sec;
556 start_time.tv_nsec = rq->perout.start.nsec;
557 fep->perout_stime = timespec64_to_ns(&start_time);
559 mutex_lock(&fep->ptp_clk_mutex);
560 if (!fep->ptp_clk_on) {
561 dev_err(&fep->pdev->dev, "Error: PTP clock is closed!\n");
562 mutex_unlock(&fep->ptp_clk_mutex);
563 return -EOPNOTSUPP;
565 spin_lock_irqsave(&fep->tmreg_lock, flags);
567 curr_time = timecounter_read(&fep->tc);
568 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
569 mutex_unlock(&fep->ptp_clk_mutex);
572 delta = fep->perout_stime - curr_time;
574 if (fep->perout_stime <= curr_time) {
575 dev_err(&fep->pdev->dev, "Start time must larger than current time!\n");
576 return -EINVAL;
579 /* Because the timer counter of FEC only has 31-bits, correspondingly,
586 timeout = ns_to_ktime(delta - NSEC_PER_SEC);
587 hrtimer_start(&fep->perout_timer, timeout, HRTIMER_MODE_REL);
592 fec_ptp_pps_disable(fep, fep->pps_channel);
597 return -EOPNOTSUPP;
606 switch (config->tx_type) {
608 fep->hwts_tx_en = 0;
611 fep->hwts_tx_en = 1;
614 return -ERANGE;
617 switch (config->rx_filter) {
619 fep->hwts_rx_en = 0;
623 fep->hwts_rx_en = 1;
624 config->rx_filter = HWTSTAMP_FILTER_ALL;
635 config->flags = 0;
636 config->tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
637 config->rx_filter = (fep->hwts_rx_en ?
642 * fec_time_keep - call timecounter_read every second to avoid timer overrun
651 mutex_lock(&fep->ptp_clk_mutex);
652 if (fep->ptp_clk_on) {
653 spin_lock_irqsave(&fep->tmreg_lock, flags);
654 timecounter_read(&fep->tc);
655 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
657 mutex_unlock(&fep->ptp_clk_mutex);
659 schedule_delayed_work(&fep->time_keep, HZ);
668 u8 channel = fep->pps_channel;
671 val = readl(fep->hwp + FEC_TCSR(channel));
676 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
678 writel(val, fep->hwp + FEC_TCSR(channel));
679 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
682 fep->next_counter = (fep->next_counter + fep->reload_period) &
683 fep->cc.mask;
686 ptp_clock_event(fep->ptp_clock, &event);
707 struct device_node *np = fep->pdev->dev.of_node;
711 fep->ptp_caps.owner = THIS_MODULE;
712 strscpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name));
714 fep->pps_channel = DEFAULT_PPS_CHANNEL;
715 of_property_read_u32(np, "fsl,pps-channel", &fep->pps_channel);
717 fep->ptp_caps.max_adj = 250000000;
718 fep->ptp_caps.n_alarm = 0;
719 fep->ptp_caps.n_ext_ts = 0;
720 fep->ptp_caps.n_per_out = 1;
721 fep->ptp_caps.n_pins = 0;
722 fep->ptp_caps.pps = 1;
723 fep->ptp_caps.adjfine = fec_ptp_adjfine;
724 fep->ptp_caps.adjtime = fec_ptp_adjtime;
725 fep->ptp_caps.gettime64 = fec_ptp_gettime;
726 fep->ptp_caps.settime64 = fec_ptp_settime;
727 fep->ptp_caps.enable = fec_ptp_enable;
729 fep->cycle_speed = clk_get_rate(fep->clk_ptp);
730 if (!fep->cycle_speed) {
731 fep->cycle_speed = NSEC_PER_SEC;
732 dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n");
734 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
736 spin_lock_init(&fep->tmreg_lock);
740 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
742 hrtimer_init(&fep->perout_timer, CLOCK_REALTIME, HRTIMER_MODE_REL);
743 fep->perout_timer.function = fec_ptp_pps_perout_handler;
752 ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt,
753 0, pdev->name, ndev);
755 dev_warn(&pdev->dev, "request for pps irq failed(%d)\n",
759 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
760 if (IS_ERR(fep->ptp_clock)) {
761 fep->ptp_clock = NULL;
762 dev_err(&pdev->dev, "ptp_clock_register failed\n");
765 schedule_delayed_work(&fep->time_keep, HZ);
773 spin_lock_irqsave(&fep->tmreg_lock, flags);
775 fep->ptp_saved_state.pps_enable = fep->pps_enable;
777 fep->ptp_saved_state.ns_phc = timecounter_read(&fep->tc);
778 fep->ptp_saved_state.ns_sys = ktime_get_ns();
780 fep->ptp_saved_state.at_corr = readl(fep->hwp + FEC_ATIME_CORR);
781 atime_inc_corr = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_CORR_MASK;
782 fep->ptp_saved_state.at_inc_corr = (u8)(atime_inc_corr >> FEC_T_INC_CORR_OFFSET);
784 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
790 u32 atime_inc = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
795 spin_lock_irqsave(&fep->tmreg_lock, flags);
798 fep->pps_enable = 0;
800 writel(fep->ptp_saved_state.at_corr, fep->hwp + FEC_ATIME_CORR);
801 atime_inc |= ((u32)fep->ptp_saved_state.at_inc_corr) << FEC_T_INC_CORR_OFFSET;
802 writel(atime_inc, fep->hwp + FEC_ATIME_INC);
804 ns = ktime_get_ns() - fep->ptp_saved_state.ns_sys + fep->ptp_saved_state.ns_phc;
805 counter = ns & fep->cc.mask;
806 writel(counter, fep->hwp + FEC_ATIME);
807 timecounter_init(&fep->tc, &fep->cc, ns);
809 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
812 if (fep->ptp_saved_state.pps_enable) {
813 /* Re-enable PPS */
823 if (fep->pps_enable)
826 cancel_delayed_work_sync(&fep->time_keep);
827 hrtimer_cancel(&fep->perout_timer);
828 if (fep->ptp_clock)
829 ptp_clock_unregister(fep->ptp_clock);