Lines Matching defs:adapter_params
436 struct adapter_params { struct
437 struct sge_params sge;
438 struct tp_params tp;
439 struct vpd_params vpd;
440 struct pf_resources pfres;
441 struct pci_params pci;
442 struct devlog_params devlog;
443 enum pcie_memwin drv_memwin;
445 unsigned int cim_la_size;
447 unsigned int sf_size; /* serial flash size in bytes */
448 unsigned int sf_nsec; /* # of flash sectors */
450 unsigned int fw_vers; /* firmware version */
451 unsigned int bs_vers; /* bootstrap version */
452 unsigned int tp_vers; /* TP microcode version */
453 unsigned int er_vers; /* expansion ROM version */
454 unsigned int scfg_vers; /* Serial Configuration version */
455 unsigned int vpd_vers; /* VPD Version */
456 u8 api_vers[7];
458 unsigned short mtus[NMTUS];
459 unsigned short a_wnd[NCCTRL_WIN];
460 unsigned short b_wnd[NCCTRL_WIN];
462 unsigned char nports; /* # of ethernet ports */
463 unsigned char portvec;
464 enum chip_type chip; /* chip code */
465 struct arch_specific_params arch; /* chip specific params */
466 unsigned char offload;
467 unsigned char crypto; /* HW capability for crypto */
468 unsigned char ethofld; /* QoS support */
470 unsigned char bypass;
471 unsigned char hash_filter;
473 unsigned int ofldq_wr_cred;
474 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
476 unsigned int nsched_cls; /* number of traffic classes */
477 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
478 unsigned int max_ird_adapter; /* Max read depth per adapter */
479 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
480 u8 fw_caps_support; /* 32-bit Port Capabilities */
481 bool filter2_wr_support; /* FW support for FILTER2_WR */
482 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
487 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
488 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
489 bool write_cmpl_support; /* FW supports WRITE_CMPL */