56 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,  in t3_wait_op_done_val()
57 			int polarity, int attempts, int delay, u32 *valp)  in t3_wait_op_done_val()
60 		u32 val = t3_read_reg(adapter, reg);  in t3_wait_op_done_val()
104 void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,  in t3_set_reg_field()
105 		      u32 val)  in t3_set_reg_field()
107 	u32 v = t3_read_reg(adapter, addr) & ~mask;  in t3_set_reg_field()
126 			     unsigned int data_reg, u32 *vals,  in t3_read_indirect()
165 			u32 val;  in t3_mc7_bd_read()
199 	u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;  in mi1_init()
200 	u32 val = F_PREEN | V_CLKDIV(clkdiv);  in mi1_init()
216 	u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);  in t3_mi1_read()
235 	u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);  in t3_mi1_write()
260 	u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);  in mi1_wr_addr()
489 	u32 val;  in t3_phy_lasi_intr_clear()
596 	u32 pad;		/* for multiple-of-4 sizing and alignment */
611 	u32 data = enable ? 0xc : 0;  in t3_seeprom_wp()
615 	ret = pci_write_vpd_any(adapter->pdev, EEPROM_STAT_ADDR, sizeof(u32),  in t3_seeprom_wp()
736 		    u32 *valp)  in sf1_read()
763 		     u32 val)  in sf1_write()
786 	u32 status;  in flash_wait_op()
815 			 unsigned int nwords, u32 *data, int byte_oriented)  in t3_read_flash()
819 	if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3))  in t3_read_flash()
852 	u32 buf[64];  in t3_write_flash()
893 int t3_get_tp_version(struct adapter *adapter, u32 *vers)  in t3_get_tp_version()
918 	u32 vers;  in t3_check_tpsram_version()
955 	u32 csum;  in t3_check_tpsram()
983 int t3_get_fw_version(struct adapter *adapter, u32 *vers)  in t3_get_fw_version()
998 	u32 vers;  in t3_check_fw_version()
1061 	u32 csum;  in t3_load_fw()
1133 static void t3_gate_rx_traffic(struct cmac *mac, u32 *rx_cfg,  in t3_gate_rx_traffic()
1134 			       u32 *rx_hash_high, u32 *rx_hash_low)  in t3_gate_rx_traffic()
1155 static void t3_open_rx_traffic(struct cmac *mac, u32 rx_cfg,  in t3_open_rx_traffic()
1156 			       u32 rx_hash_high, u32 rx_hash_low)  in t3_open_rx_traffic()
1186 		u32 rx_cfg, rx_hash_high, rx_hash_low;  in t3_link_changed()
1187 		u32 status;  in t3_link_changed()
1239 	u32 rx_cfg, rx_hash_high, rx_hash_low;  in t3_link_fault()
1729 	u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);  in mc7_intr_handler()
1758 		u32 addr = 0;  in mc7_intr_handler()
1788 	u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) &  in mac_intr_handler()
1830 	u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);  in t3_phy_intr_handler()
1859 	u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);  in t3_slow_intr_handler()
2233 		     V_FL_BASE_HI((u32) base_addr) |  in t3_sge_init_flcntxt()
2278 		     V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen));  in t3_sge_init_rspcntxt()
2312 		     V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) |  in t3_sge_init_cqcntxt()
2431 	u32 val;  in t3_sge_cqcntxt_op()
2477 			u32 val = i << 16;  in t3_config_rss()
2600 				  u32 val)  in tp_wr_indirect()
2718 	u32 val;  in t3_tp_set_coalescing_size()
2874 	t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps,  in t3_tp_get_mib_stats()
2875 			 sizeof(*tps) / sizeof(u32), 0);  in t3_tp_get_mib_stats()
2935 	u32 addr, key[4], mask[4];  in t3_config_trace_filter()
3120 static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val)  in wrreg_wait()
3143 	u32 val;  in mc7_init()
3309 int t3_init_hw(struct adapter *adapter, u32 fw_params)  in t3_init_hw()
3394 	u32 pci_mode;  in get_pci_mode()
3451 static unsigned int mc7_calc_size(u32 cfg)  in mc7_calc_size()
3465 	u32 cfg;  in mc7_prep()
3498 	u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2);  in early_hw_init()