Lines Matching refs:adapter
38 static void t3_port_intr_clear(struct adapter *adapter, int idx);
56 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, in t3_wait_op_done_val() argument
60 u32 val = t3_read_reg(adapter, reg); in t3_wait_op_done_val()
85 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, in t3_write_regs() argument
89 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
104 void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, in t3_set_reg_field() argument
107 u32 v = t3_read_reg(adapter, addr) & ~mask; in t3_set_reg_field()
109 t3_write_reg(adapter, addr, v | val); in t3_set_reg_field()
110 t3_read_reg(adapter, addr); /* flush */ in t3_set_reg_field()
125 static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg, in t3_read_indirect()
153 struct adapter *adap = mc7->adapter; in t3_mc7_bd_read()
197 static void mi1_init(struct adapter *adap, const struct adapter_info *ai) in mi1_init()
214 struct adapter *adapter = pi->adapter; in t3_mi1_read() local
218 mutex_lock(&adapter->mdio_lock); in t3_mi1_read()
219 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); in t3_mi1_read()
220 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_read()
221 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); in t3_mi1_read()
222 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in t3_mi1_read()
224 ret = t3_read_reg(adapter, A_MI1_DATA); in t3_mi1_read()
225 mutex_unlock(&adapter->mdio_lock); in t3_mi1_read()
233 struct adapter *adapter = pi->adapter; in t3_mi1_write() local
237 mutex_lock(&adapter->mdio_lock); in t3_mi1_write()
238 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); in t3_mi1_write()
239 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_write()
240 t3_write_reg(adapter, A_MI1_DATA, val); in t3_mi1_write()
241 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in t3_mi1_write()
242 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in t3_mi1_write()
243 mutex_unlock(&adapter->mdio_lock); in t3_mi1_write()
257 static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr, in mi1_wr_addr() argument
262 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); in mi1_wr_addr()
263 t3_write_reg(adapter, A_MI1_ADDR, addr); in mi1_wr_addr()
264 t3_write_reg(adapter, A_MI1_DATA, reg_addr); in mi1_wr_addr()
265 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); in mi1_wr_addr()
266 return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_wr_addr()
277 struct adapter *adapter = pi->adapter; in mi1_ext_read() local
280 mutex_lock(&adapter->mdio_lock); in mi1_ext_read()
281 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr); in mi1_ext_read()
283 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3)); in mi1_ext_read()
284 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_ext_read()
287 ret = t3_read_reg(adapter, A_MI1_DATA); in mi1_ext_read()
289 mutex_unlock(&adapter->mdio_lock); in mi1_ext_read()
297 struct adapter *adapter = pi->adapter; in mi1_ext_write() local
300 mutex_lock(&adapter->mdio_lock); in mi1_ext_write()
301 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr); in mi1_ext_write()
303 t3_write_reg(adapter, A_MI1_DATA, val); in mi1_ext_write()
304 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in mi1_ext_write()
305 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_ext_write()
308 mutex_unlock(&adapter->mdio_lock); in mi1_ext_write()
549 int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
609 int t3_seeprom_wp(struct adapter *adapter, int enable) in t3_seeprom_wp() argument
615 ret = pci_write_vpd_any(adapter->pdev, EEPROM_STAT_ADDR, sizeof(u32), in t3_seeprom_wp()
646 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) in get_vpd_params() argument
656 ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val); in get_vpd_params()
661 ret = pci_read_vpd(adapter->pdev, addr, sizeof(vpd), &vpd); in get_vpd_params()
683 if (adapter->params.rev == 0 && !vpd.port0_data[0]) { in get_vpd_params()
684 p->port_type[0] = uses_xaui(adapter) ? 1 : 2; in get_vpd_params()
685 p->port_type[1] = uses_xaui(adapter) ? 6 : 2; in get_vpd_params()
735 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, in sf1_read() argument
742 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_read()
744 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); in sf1_read()
745 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); in sf1_read()
747 *valp = t3_read_reg(adapter, A_SF_DATA); in sf1_read()
762 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, in sf1_write() argument
767 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_write()
769 t3_write_reg(adapter, A_SF_DATA, val); in sf1_write()
770 t3_write_reg(adapter, A_SF_OP, in sf1_write()
772 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); in sf1_write()
783 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) in flash_wait_op() argument
789 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 || in flash_wait_op()
790 (ret = sf1_read(adapter, 1, 0, &status)) != 0) in flash_wait_op()
814 static int t3_read_flash(struct adapter *adapter, unsigned int addr, in t3_read_flash() argument
824 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 || in t3_read_flash()
825 (ret = sf1_read(adapter, 1, 1, data)) != 0) in t3_read_flash()
829 ret = sf1_read(adapter, 4, nwords > 1, data); in t3_read_flash()
848 static int t3_write_flash(struct adapter *adapter, unsigned int addr, in t3_write_flash() argument
860 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || in t3_write_flash()
861 (ret = sf1_write(adapter, 4, 1, val)) != 0) in t3_write_flash()
869 ret = sf1_write(adapter, c, c != left, val); in t3_write_flash()
873 if ((ret = flash_wait_op(adapter, 5, 1)) != 0) in t3_write_flash()
877 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); in t3_write_flash()
893 int t3_get_tp_version(struct adapter *adapter, u32 *vers) in t3_get_tp_version() argument
898 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0); in t3_get_tp_version()
899 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0, in t3_get_tp_version()
904 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); in t3_get_tp_version()
915 int t3_check_tpsram_version(struct adapter *adapter) in t3_check_tpsram_version() argument
921 if (adapter->params.rev == T3_REV_A) in t3_check_tpsram_version()
925 ret = t3_get_tp_version(adapter, &vers); in t3_check_tpsram_version()
935 CH_ERR(adapter, "found wrong TP version (%u.%u), " in t3_check_tpsram_version()
952 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram, in t3_check_tpsram() argument
963 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n", in t3_check_tpsram()
983 int t3_get_fw_version(struct adapter *adapter, u32 *vers) in t3_get_fw_version() argument
985 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0); in t3_get_fw_version()
995 int t3_check_fw_version(struct adapter *adapter) in t3_check_fw_version() argument
1001 ret = t3_get_fw_version(adapter, &vers); in t3_check_fw_version()
1013 CH_WARN(adapter, "found old FW minor version(%u.%u), " in t3_check_fw_version()
1017 CH_WARN(adapter, "found newer FW version(%u.%u), " in t3_check_fw_version()
1033 static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end) in t3_flash_erase_sectors() argument
1038 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || in t3_flash_erase_sectors()
1039 (ret = sf1_write(adapter, 4, 0, in t3_flash_erase_sectors()
1041 (ret = flash_wait_op(adapter, 5, 500)) != 0) in t3_flash_erase_sectors()
1059 int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size) in t3_load_fw() argument
1074 CH_ERR(adapter, "corrupted firmware image, checksum %u\n", in t3_load_fw()
1079 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector); in t3_load_fw()
1087 ret = t3_write_flash(adapter, addr, chunk_size, fw_data); in t3_load_fw()
1096 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data); in t3_load_fw()
1099 CH_ERR(adapter, "firmware download failed, error %d\n", ret); in t3_load_fw()
1115 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, in t3_cim_ctl_blk_read()
1140 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG); in t3_gate_rx_traffic()
1141 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG, in t3_gate_rx_traffic()
1145 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH); in t3_gate_rx_traffic()
1146 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0); in t3_gate_rx_traffic()
1148 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW); in t3_gate_rx_traffic()
1149 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0); in t3_gate_rx_traffic()
1159 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG, in t3_open_rx_traffic()
1162 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high); in t3_open_rx_traffic()
1163 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low); in t3_open_rx_traffic()
1175 void t3_link_changed(struct adapter *adapter, int port_id) in t3_link_changed() argument
1178 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_link_changed()
1189 t3_xgm_intr_enable(adapter, port_id); in t3_link_changed()
1191 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_changed()
1194 status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_link_changed()
1211 if (link_ok != lc->link_ok && adapter->params.rev > 0 && in t3_link_changed()
1212 uses_xaui(adapter)) { in t3_link_changed()
1215 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_changed()
1228 t3_os_link_changed(adapter, port_id, link_ok && !pi->link_fault, in t3_link_changed()
1232 void t3_link_fault(struct adapter *adapter, int port_id) in t3_link_fault() argument
1234 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_link_fault()
1243 if (adapter->params.rev > 0 && uses_xaui(adapter)) in t3_link_fault()
1244 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0); in t3_link_fault()
1246 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_fault()
1251 link_fault = t3_read_reg(adapter, in t3_link_fault()
1267 t3_os_link_fault(adapter, port_id, 0); in t3_link_fault()
1274 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_fault()
1281 t3_os_link_fault(adapter, port_id, link_ok); in t3_link_fault()
1338 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on) in t3_set_vlan_accel() argument
1340 t3_set_reg_field(adapter, A_TP_OUT_CONFIG, in t3_set_vlan_accel()
1367 static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, in t3_handle_intr_status() argument
1373 unsigned int status = t3_read_reg(adapter, reg) & mask; in t3_handle_intr_status()
1380 CH_ALERT(adapter, "%s (0x%x)\n", in t3_handle_intr_status()
1384 CH_WARN(adapter, "%s (0x%x)\n", in t3_handle_intr_status()
1390 t3_write_reg(adapter, reg, status); in t3_handle_intr_status()
1455 static void pci_intr_handler(struct adapter *adapter) in pci_intr_handler() argument
1483 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK, in pci_intr_handler()
1484 pcix1_intr_info, adapter->irq_stats)) in pci_intr_handler()
1485 t3_fatal_err(adapter); in pci_intr_handler()
1491 static void pcie_intr_handler(struct adapter *adapter) in pcie_intr_handler() argument
1513 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR) in pcie_intr_handler()
1514 CH_ALERT(adapter, "PEX error code 0x%x\n", in pcie_intr_handler()
1515 t3_read_reg(adapter, A_PCIE_PEX_ERR)); in pcie_intr_handler()
1517 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK, in pcie_intr_handler()
1518 pcie_intr_info, adapter->irq_stats)) in pcie_intr_handler()
1519 t3_fatal_err(adapter); in pcie_intr_handler()
1525 static void tp_intr_handler(struct adapter *adapter) in tp_intr_handler() argument
1541 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, in tp_intr_handler()
1542 adapter->params.rev < T3_REV_C ? in tp_intr_handler()
1544 t3_fatal_err(adapter); in tp_intr_handler()
1550 static void cim_intr_handler(struct adapter *adapter) in cim_intr_handler() argument
1580 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff, in cim_intr_handler()
1582 t3_fatal_err(adapter); in cim_intr_handler()
1588 static void ulprx_intr_handler(struct adapter *adapter) in ulprx_intr_handler() argument
1602 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff, in ulprx_intr_handler()
1604 t3_fatal_err(adapter); in ulprx_intr_handler()
1610 static void ulptx_intr_handler(struct adapter *adapter) in ulptx_intr_handler() argument
1621 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff, in ulptx_intr_handler()
1622 ulptx_intr_info, adapter->irq_stats)) in ulptx_intr_handler()
1623 t3_fatal_err(adapter); in ulptx_intr_handler()
1638 static void pmtx_intr_handler(struct adapter *adapter) in pmtx_intr_handler() argument
1651 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff, in pmtx_intr_handler()
1653 t3_fatal_err(adapter); in pmtx_intr_handler()
1668 static void pmrx_intr_handler(struct adapter *adapter) in pmrx_intr_handler() argument
1681 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff, in pmrx_intr_handler()
1683 t3_fatal_err(adapter); in pmrx_intr_handler()
1689 static void cplsw_intr_handler(struct adapter *adapter) in cplsw_intr_handler() argument
1701 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff, in cplsw_intr_handler()
1703 t3_fatal_err(adapter); in cplsw_intr_handler()
1709 static void mps_intr_handler(struct adapter *adapter) in mps_intr_handler() argument
1716 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff, in mps_intr_handler()
1718 t3_fatal_err(adapter); in mps_intr_handler()
1728 struct adapter *adapter = mc7->adapter; in mc7_intr_handler() local
1729 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); in mc7_intr_handler()
1733 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, " in mc7_intr_handler()
1735 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR), in mc7_intr_handler()
1736 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0), in mc7_intr_handler()
1737 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1), in mc7_intr_handler()
1738 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2)); in mc7_intr_handler()
1743 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, " in mc7_intr_handler()
1745 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR), in mc7_intr_handler()
1746 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0), in mc7_intr_handler()
1747 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1), in mc7_intr_handler()
1748 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2)); in mc7_intr_handler()
1753 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n", in mc7_intr_handler()
1760 if (adapter->params.rev > 0) in mc7_intr_handler()
1761 addr = t3_read_reg(adapter, in mc7_intr_handler()
1764 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n", in mc7_intr_handler()
1769 t3_fatal_err(adapter); in mc7_intr_handler()
1771 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); in mc7_intr_handler()
1779 static int mac_intr_handler(struct adapter *adap, unsigned int idx) in mac_intr_handler()
1828 int t3_phy_intr_handler(struct adapter *adapter) in t3_phy_intr_handler() argument
1830 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); in t3_phy_intr_handler()
1832 for_each_port(adapter, i) { in t3_phy_intr_handler()
1833 struct port_info *p = adap2pinfo(adapter, i); in t3_phy_intr_handler()
1838 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) { in t3_phy_intr_handler()
1842 t3_link_changed(adapter, i); in t3_phy_intr_handler()
1846 t3_os_phymod_changed(adapter, i); in t3_phy_intr_handler()
1850 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause); in t3_phy_intr_handler()
1857 int t3_slow_intr_handler(struct adapter *adapter) in t3_slow_intr_handler() argument
1859 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0); in t3_slow_intr_handler()
1861 cause &= adapter->slow_intr_mask; in t3_slow_intr_handler()
1865 if (is_pcie(adapter)) in t3_slow_intr_handler()
1866 pcie_intr_handler(adapter); in t3_slow_intr_handler()
1868 pci_intr_handler(adapter); in t3_slow_intr_handler()
1871 t3_sge_err_intr_handler(adapter); in t3_slow_intr_handler()
1873 mc7_intr_handler(&adapter->pmrx); in t3_slow_intr_handler()
1875 mc7_intr_handler(&adapter->pmtx); in t3_slow_intr_handler()
1877 mc7_intr_handler(&adapter->cm); in t3_slow_intr_handler()
1879 cim_intr_handler(adapter); in t3_slow_intr_handler()
1881 tp_intr_handler(adapter); in t3_slow_intr_handler()
1883 ulprx_intr_handler(adapter); in t3_slow_intr_handler()
1885 ulptx_intr_handler(adapter); in t3_slow_intr_handler()
1887 pmrx_intr_handler(adapter); in t3_slow_intr_handler()
1889 pmtx_intr_handler(adapter); in t3_slow_intr_handler()
1891 cplsw_intr_handler(adapter); in t3_slow_intr_handler()
1893 mps_intr_handler(adapter); in t3_slow_intr_handler()
1895 t3_mc5_intr_handler(&adapter->mc5); in t3_slow_intr_handler()
1897 mac_intr_handler(adapter, 0); in t3_slow_intr_handler()
1899 mac_intr_handler(adapter, 1); in t3_slow_intr_handler()
1901 t3_os_ext_intr_handler(adapter); in t3_slow_intr_handler()
1904 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause); in t3_slow_intr_handler()
1905 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ in t3_slow_intr_handler()
1909 static unsigned int calc_gpio_intr(struct adapter *adap) in calc_gpio_intr()
1928 void t3_intr_enable(struct adapter *adapter) in t3_intr_enable() argument
1945 adapter->slow_intr_mask = PL_INTR_MASK; in t3_intr_enable()
1947 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0); in t3_intr_enable()
1948 t3_write_reg(adapter, A_TP_INT_ENABLE, in t3_intr_enable()
1949 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff); in t3_intr_enable()
1951 if (adapter->params.rev > 0) { in t3_intr_enable()
1952 t3_write_reg(adapter, A_CPL_INTR_ENABLE, in t3_intr_enable()
1954 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, in t3_intr_enable()
1958 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK); in t3_intr_enable()
1959 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); in t3_intr_enable()
1962 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter)); in t3_intr_enable()
1964 if (is_pcie(adapter)) in t3_intr_enable()
1965 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); in t3_intr_enable()
1967 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK); in t3_intr_enable()
1968 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); in t3_intr_enable()
1969 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ in t3_intr_enable()
1979 void t3_intr_disable(struct adapter *adapter) in t3_intr_disable() argument
1981 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0); in t3_intr_disable()
1982 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ in t3_intr_disable()
1983 adapter->slow_intr_mask = 0; in t3_intr_disable()
1992 void t3_intr_clear(struct adapter *adapter) in t3_intr_clear() argument
2015 for_each_port(adapter, i) in t3_intr_clear()
2016 t3_port_intr_clear(adapter, i); in t3_intr_clear()
2019 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); in t3_intr_clear()
2021 if (is_pcie(adapter)) in t3_intr_clear()
2022 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); in t3_intr_clear()
2023 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); in t3_intr_clear()
2024 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ in t3_intr_clear()
2027 void t3_xgm_intr_enable(struct adapter *adapter, int idx) in t3_xgm_intr_enable() argument
2029 struct port_info *pi = adap2pinfo(adapter, idx); in t3_xgm_intr_enable()
2031 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, in t3_xgm_intr_enable()
2035 void t3_xgm_intr_disable(struct adapter *adapter, int idx) in t3_xgm_intr_disable() argument
2037 struct port_info *pi = adap2pinfo(adapter, idx); in t3_xgm_intr_disable()
2039 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, in t3_xgm_intr_disable()
2051 void t3_port_intr_enable(struct adapter *adapter, int idx) in t3_port_intr_enable() argument
2053 struct cphy *phy = &adap2pinfo(adapter, idx)->phy; in t3_port_intr_enable()
2055 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK); in t3_port_intr_enable()
2056 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */ in t3_port_intr_enable()
2068 void t3_port_intr_disable(struct adapter *adapter, int idx) in t3_port_intr_disable() argument
2070 struct cphy *phy = &adap2pinfo(adapter, idx)->phy; in t3_port_intr_disable()
2072 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0); in t3_port_intr_disable()
2073 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */ in t3_port_intr_disable()
2085 static void t3_port_intr_clear(struct adapter *adapter, int idx) in t3_port_intr_clear() argument
2087 struct cphy *phy = &adap2pinfo(adapter, idx)->phy; in t3_port_intr_clear()
2089 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff); in t3_port_intr_clear()
2090 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */ in t3_port_intr_clear()
2105 static int t3_sge_write_context(struct adapter *adapter, unsigned int id, in t3_sge_write_context() argument
2115 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2116 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2117 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff); in t3_sge_write_context()
2118 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2120 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2121 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2122 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); in t3_sge_write_context()
2123 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2125 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_write_context()
2127 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_write_context()
2142 static int clear_sge_ctxt(struct adapter *adap, unsigned int id, in clear_sge_ctxt()
2176 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, in t3_sge_init_ecntxt() argument
2185 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_ecntxt()
2189 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) | in t3_sge_init_ecntxt()
2191 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) | in t3_sge_init_ecntxt()
2194 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr); in t3_sge_init_ecntxt()
2196 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_ecntxt()
2200 return t3_sge_write_context(adapter, id, F_EGRESS); in t3_sge_init_ecntxt()
2219 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, in t3_sge_init_flcntxt() argument
2226 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_flcntxt()
2230 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr); in t3_sge_init_flcntxt()
2232 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, in t3_sge_init_flcntxt()
2235 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) | in t3_sge_init_flcntxt()
2238 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_flcntxt()
2241 return t3_sge_write_context(adapter, id, F_FREELIST); in t3_sge_init_flcntxt()
2259 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, in t3_sge_init_rspcntxt() argument
2267 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_rspcntxt()
2271 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) | in t3_sge_init_rspcntxt()
2273 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_rspcntxt()
2277 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_rspcntxt()
2279 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres); in t3_sge_init_rspcntxt()
2280 return t3_sge_write_context(adapter, id, F_RESPONSEQ); in t3_sge_init_rspcntxt()
2298 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, in t3_sge_init_cqcntxt() argument
2304 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_cqcntxt()
2308 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size)); in t3_sge_init_cqcntxt()
2309 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_cqcntxt()
2311 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_cqcntxt()
2315 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | in t3_sge_init_cqcntxt()
2317 return t3_sge_write_context(adapter, id, F_CQ); in t3_sge_init_cqcntxt()
2329 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable) in t3_sge_enable_ecntxt() argument
2331 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_enable_ecntxt()
2334 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_enable_ecntxt()
2335 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_enable_ecntxt()
2336 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_enable_ecntxt()
2337 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID); in t3_sge_enable_ecntxt()
2338 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable)); in t3_sge_enable_ecntxt()
2339 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_enable_ecntxt()
2341 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_enable_ecntxt()
2353 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id) in t3_sge_disable_fl() argument
2355 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_fl()
2358 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_disable_fl()
2359 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_fl()
2360 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE)); in t3_sge_disable_fl()
2361 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_fl()
2362 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0); in t3_sge_disable_fl()
2363 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_fl()
2365 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_fl()
2377 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id) in t3_sge_disable_rspcntxt() argument
2379 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_rspcntxt()
2382 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_rspcntxt()
2383 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_rspcntxt()
2384 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_rspcntxt()
2385 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_rspcntxt()
2386 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_rspcntxt()
2387 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_rspcntxt()
2389 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_rspcntxt()
2401 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id) in t3_sge_disable_cqcntxt() argument
2403 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_cqcntxt()
2406 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_cqcntxt()
2407 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_cqcntxt()
2408 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_cqcntxt()
2409 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_cqcntxt()
2410 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_cqcntxt()
2411 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_cqcntxt()
2413 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_cqcntxt()
2428 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, in t3_sge_cqcntxt_op() argument
2433 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_cqcntxt_op()
2436 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16); in t3_sge_cqcntxt_op()
2437 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) | in t3_sge_cqcntxt_op()
2439 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_cqcntxt_op()
2444 if (adapter->params.rev > 0) in t3_sge_cqcntxt_op()
2447 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2449 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2453 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0)); in t3_sge_cqcntxt_op()
2470 void t3_config_rss(struct adapter *adapter, unsigned int rss_config, in t3_config_rss() argument
2484 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val); in t3_config_rss()
2489 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, in t3_config_rss()
2495 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config); in t3_config_rss()
2505 void t3_tp_set_offload_mode(struct adapter *adap, int enable) in t3_tp_set_offload_mode()
2541 static void partition_mem(struct adapter *adap, const struct tp_params *p) in partition_mem()
2599 static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr, in tp_wr_indirect()
2606 static void tp_config(struct adapter *adap, const struct tp_params *p) in tp_config()
2671 static void tp_set_timers(struct adapter *adap, unsigned int core_clk) in tp_set_timers()
2715 static int t3_tp_set_coalescing_size(struct adapter *adap, in t3_tp_set_coalescing_size()
2746 static void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size) in t3_tp_set_max_rxsize()
2832 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], in t3_load_mtus()
2872 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps) in t3_tp_get_mib_stats()
2889 static void ulp_config(struct adapter *adap, const struct tp_params *p) in ulp_config()
2910 int t3_set_proto_sram(struct adapter *adap, const u8 *data) in t3_set_proto_sram()
2931 void t3_config_trace_filter(struct adapter *adapter, in t3_config_trace_filter() argument
2953 tp_wr_indirect(adapter, addr++, key[0]); in t3_config_trace_filter()
2954 tp_wr_indirect(adapter, addr++, mask[0]); in t3_config_trace_filter()
2955 tp_wr_indirect(adapter, addr++, key[1]); in t3_config_trace_filter()
2956 tp_wr_indirect(adapter, addr++, mask[1]); in t3_config_trace_filter()
2957 tp_wr_indirect(adapter, addr++, key[2]); in t3_config_trace_filter()
2958 tp_wr_indirect(adapter, addr++, mask[2]); in t3_config_trace_filter()
2959 tp_wr_indirect(adapter, addr++, key[3]); in t3_config_trace_filter()
2960 tp_wr_indirect(adapter, addr, mask[3]); in t3_config_trace_filter()
2961 t3_read_reg(adapter, A_TP_PIO_DATA); in t3_config_trace_filter()
2972 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched) in t3_config_sched()
3008 static int tp_init(struct adapter *adap, const struct tp_params *p) in tp_init()
3033 static void chan_init_hw(struct adapter *adap, unsigned int chan_map) in chan_init_hw()
3063 static int calibrate_xgm(struct adapter *adapter) in calibrate_xgm() argument
3065 if (uses_xaui(adapter)) { in calibrate_xgm()
3069 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0); in calibrate_xgm()
3070 t3_read_reg(adapter, A_XGM_XAUI_IMP); in calibrate_xgm()
3072 v = t3_read_reg(adapter, A_XGM_XAUI_IMP); in calibrate_xgm()
3074 t3_write_reg(adapter, A_XGM_XAUI_IMP, in calibrate_xgm()
3079 CH_ERR(adapter, "MAC calibration failed\n"); in calibrate_xgm()
3082 t3_write_reg(adapter, A_XGM_RGMII_IMP, in calibrate_xgm()
3084 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, in calibrate_xgm()
3090 static void calibrate_xgm_t3b(struct adapter *adapter) in calibrate_xgm_t3b() argument
3092 if (!uses_xaui(adapter)) { in calibrate_xgm_t3b()
3093 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET | in calibrate_xgm_t3b()
3095 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0); in calibrate_xgm_t3b()
3096 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, in calibrate_xgm_t3b()
3098 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, in calibrate_xgm_t3b()
3100 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0); in calibrate_xgm_t3b()
3101 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE); in calibrate_xgm_t3b()
3120 static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val) in wrreg_wait() argument
3122 t3_write_reg(adapter, addr, val); in wrreg_wait()
3123 t3_read_reg(adapter, addr); /* flush */ in wrreg_wait()
3124 if (!(t3_read_reg(adapter, addr) & F_BUSY)) in wrreg_wait()
3126 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr); in wrreg_wait()
3145 struct adapter *adapter = mc7->adapter; in mc7_init() local
3151 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_init()
3156 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); in mc7_init()
3157 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3161 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); in mc7_init()
3162 t3_read_reg(adapter, mc7->offset + A_MC7_CAL); in mc7_init()
3164 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & in mc7_init()
3166 CH_ERR(adapter, "%s MC7 calibration timed out\n", in mc7_init()
3172 t3_write_reg(adapter, mc7->offset + A_MC7_PARM, in mc7_init()
3178 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, in mc7_init()
3180 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3183 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, in mc7_init()
3188 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
3189 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) || in mc7_init()
3190 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) || in mc7_init()
3191 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
3195 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); in mc7_init()
3196 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0); in mc7_init()
3200 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
3201 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
3202 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
3203 wrreg_wait(adapter, mc7->offset + A_MC7_MODE, in mc7_init()
3205 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || in mc7_init()
3206 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
3213 t3_write_reg(adapter, mc7->offset + A_MC7_REF, in mc7_init()
3215 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ in mc7_init()
3217 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN); in mc7_init()
3218 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); in mc7_init()
3219 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); in mc7_init()
3220 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, in mc7_init()
3222 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); in mc7_init()
3223 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ in mc7_init()
3228 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); in mc7_init()
3231 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name); in mc7_init()
3236 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); in mc7_init()
3243 static void config_pcie(struct adapter *adap) in config_pcie()
3309 int t3_init_hw(struct adapter *adapter, u32 fw_params) in t3_init_hw() argument
3312 const struct vpd_params *vpd = &adapter->params.vpd; in t3_init_hw()
3314 if (adapter->params.rev > 0) in t3_init_hw()
3315 calibrate_xgm_t3b(adapter); in t3_init_hw()
3316 else if (calibrate_xgm(adapter)) in t3_init_hw()
3320 partition_mem(adapter, &adapter->params.tp); in t3_init_hw()
3322 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
3323 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
3324 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
3325 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers, in t3_init_hw()
3326 adapter->params.mc5.nfilters, in t3_init_hw()
3327 adapter->params.mc5.nroutes)) in t3_init_hw()
3331 if (clear_sge_ctxt(adapter, i, F_CQ)) in t3_init_hw()
3335 if (tp_init(adapter, &adapter->params.tp)) in t3_init_hw()
3338 t3_tp_set_coalescing_size(adapter, in t3_init_hw()
3339 min(adapter->params.sge.max_pkt_size, in t3_init_hw()
3341 t3_tp_set_max_rxsize(adapter, in t3_init_hw()
3342 min(adapter->params.sge.max_pkt_size, 16384U)); in t3_init_hw()
3343 ulp_config(adapter, &adapter->params.tp); in t3_init_hw()
3345 if (is_pcie(adapter)) in t3_init_hw()
3346 config_pcie(adapter); in t3_init_hw()
3348 t3_set_reg_field(adapter, A_PCIX_CFG, 0, in t3_init_hw()
3351 if (adapter->params.rev == T3_REV_C) in t3_init_hw()
3352 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0, in t3_init_hw()
3355 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); in t3_init_hw()
3356 t3_write_reg(adapter, A_PM1_RX_MODE, 0); in t3_init_hw()
3357 t3_write_reg(adapter, A_PM1_TX_MODE, 0); in t3_init_hw()
3358 chan_init_hw(adapter, adapter->params.chan_map); in t3_init_hw()
3359 t3_sge_init(adapter, &adapter->params.sge); in t3_init_hw()
3360 t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN); in t3_init_hw()
3362 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); in t3_init_hw()
3364 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
3365 t3_write_reg(adapter, A_CIM_BOOT_CFG, in t3_init_hw()
3367 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ in t3_init_hw()
3372 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); in t3_init_hw()
3374 CH_ERR(adapter, "uP initialization timed out\n"); in t3_init_hw()
3391 static void get_pci_mode(struct adapter *adapter, struct pci_params *p) in get_pci_mode() argument
3396 if (pci_is_pcie(adapter->pdev)) { in get_pci_mode()
3400 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); in get_pci_mode()
3405 pci_mode = t3_read_reg(adapter, A_PCIX_MODE); in get_pci_mode()
3462 static void mc7_prep(struct adapter *adapter, struct mc7 *mc7, in mc7_prep() argument
3467 mc7->adapter = adapter; in mc7_prep()
3470 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_prep()
3475 static void mac_prep(struct cmac *mac, struct adapter *adapter, int index) in mac_prep() argument
3479 mac->adapter = adapter; in mac_prep()
3480 pci_read_config_word(adapter->pdev, 0x2, &devid); in mac_prep()
3482 if (devid == 0x37 && !adapter->params.vpd.xauicfg[1]) in mac_prep()
3487 if (adapter->params.rev == 0 && uses_xaui(adapter)) { in mac_prep()
3488 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, in mac_prep()
3489 is_10G(adapter) ? 0x2901c04 : 0x2301c04); in mac_prep()
3490 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset, in mac_prep()
3495 static void early_hw_init(struct adapter *adapter, in early_hw_init() argument
3498 u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2); in early_hw_init()
3500 mi1_init(adapter, ai); in early_hw_init()
3501 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ in early_hw_init()
3502 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); in early_hw_init()
3503 t3_write_reg(adapter, A_T3DBG_GPIO_EN, in early_hw_init()
3505 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); in early_hw_init()
3506 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); in early_hw_init()
3508 if (adapter->params.rev == 0 || !uses_xaui(adapter)) in early_hw_init()
3512 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
3513 t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
3516 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
3517 t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
3518 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); in early_hw_init()
3519 t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
3527 int t3_reset_adapter(struct adapter *adapter) in t3_reset_adapter() argument
3530 adapter->params.rev < T3_REV_B2 && is_pcie(adapter); in t3_reset_adapter()
3534 pci_save_state(adapter->pdev); in t3_reset_adapter()
3535 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); in t3_reset_adapter()
3543 pci_read_config_word(adapter->pdev, 0x00, &devid); in t3_reset_adapter()
3552 pci_restore_state(adapter->pdev); in t3_reset_adapter()
3556 static int init_parity(struct adapter *adap) in init_parity()
3591 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, in t3_prep_adapter() argument
3597 get_pci_mode(adapter, &adapter->params.pci); in t3_prep_adapter()
3599 adapter->params.info = ai; in t3_prep_adapter()
3600 adapter->params.nports = ai->nports0 + ai->nports1; in t3_prep_adapter()
3601 adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1); in t3_prep_adapter()
3602 adapter->params.rev = t3_read_reg(adapter, A_PL_REV); in t3_prep_adapter()
3611 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
3612 adapter->params.stats_update_period = is_10G(adapter) ? in t3_prep_adapter()
3614 adapter->params.pci.vpd_cap_addr = in t3_prep_adapter()
3615 pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD); in t3_prep_adapter()
3616 if (!adapter->params.pci.vpd_cap_addr) in t3_prep_adapter()
3618 ret = get_vpd_params(adapter, &adapter->params.vpd); in t3_prep_adapter()
3622 if (reset && t3_reset_adapter(adapter)) in t3_prep_adapter()
3625 t3_sge_prep(adapter, &adapter->params.sge); in t3_prep_adapter()
3627 if (adapter->params.vpd.mclk) { in t3_prep_adapter()
3628 struct tp_params *p = &adapter->params.tp; in t3_prep_adapter()
3630 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX"); in t3_prep_adapter()
3631 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX"); in t3_prep_adapter()
3632 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM"); in t3_prep_adapter()
3634 p->nchan = adapter->params.chan_map == 3 ? 2 : 1; in t3_prep_adapter()
3635 p->pmrx_size = t3_mc7_size(&adapter->pmrx); in t3_prep_adapter()
3636 p->pmtx_size = t3_mc7_size(&adapter->pmtx); in t3_prep_adapter()
3637 p->cm_size = t3_mc7_size(&adapter->cm); in t3_prep_adapter()
3641 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024; in t3_prep_adapter()
3645 adapter->params.rev > 0 ? 12 : 6; in t3_prep_adapter()
3648 adapter->params.offload = t3_mc7_size(&adapter->pmrx) && in t3_prep_adapter()
3649 t3_mc7_size(&adapter->pmtx) && in t3_prep_adapter()
3650 t3_mc7_size(&adapter->cm); in t3_prep_adapter()
3652 if (is_offload(adapter)) { in t3_prep_adapter()
3653 adapter->params.mc5.nservers = DEFAULT_NSERVERS; in t3_prep_adapter()
3654 adapter->params.mc5.nfilters = adapter->params.rev > 0 ? in t3_prep_adapter()
3656 adapter->params.mc5.nroutes = 0; in t3_prep_adapter()
3657 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT); in t3_prep_adapter()
3659 init_mtus(adapter->params.mtus); in t3_prep_adapter()
3660 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t3_prep_adapter()
3663 early_hw_init(adapter, ai); in t3_prep_adapter()
3664 ret = init_parity(adapter); in t3_prep_adapter()
3668 for_each_port(adapter, i) { in t3_prep_adapter()
3671 struct port_info *p = adap2pinfo(adapter, i); in t3_prep_adapter()
3673 while (!adapter->params.vpd.port_type[++j]) in t3_prep_adapter()
3676 pti = &port_types[adapter->params.vpd.port_type[j]]; in t3_prep_adapter()
3678 CH_ALERT(adapter, "Invalid port type index %d\n", in t3_prep_adapter()
3679 adapter->params.vpd.port_type[j]); in t3_prep_adapter()
3683 p->phy.mdio.dev = adapter->port[i]; in t3_prep_adapter()
3684 ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j, in t3_prep_adapter()
3688 mac_prep(&p->mac, adapter, j); in t3_prep_adapter()
3695 memcpy(hw_addr, adapter->params.vpd.eth_base, 5); in t3_prep_adapter()
3696 hw_addr[5] = adapter->params.vpd.eth_base[5] + i; in t3_prep_adapter()
3698 eth_hw_addr_set(adapter->port[i], hw_addr); in t3_prep_adapter()
3708 adapter->params.linkpoll_period > 10) in t3_prep_adapter()
3709 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
3715 void t3_led_ready(struct adapter *adapter) in t3_led_ready() argument
3717 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, in t3_led_ready()
3721 int t3_replay_prep_adapter(struct adapter *adapter) in t3_replay_prep_adapter() argument
3723 const struct adapter_info *ai = adapter->params.info; in t3_replay_prep_adapter()
3727 early_hw_init(adapter, ai); in t3_replay_prep_adapter()
3728 ret = init_parity(adapter); in t3_replay_prep_adapter()
3732 for_each_port(adapter, i) { in t3_replay_prep_adapter()
3734 struct port_info *p = adap2pinfo(adapter, i); in t3_replay_prep_adapter()
3736 while (!adapter->params.vpd.port_type[++j]) in t3_replay_prep_adapter()
3739 pti = &port_types[adapter->params.vpd.port_type[j]]; in t3_replay_prep_adapter()
3740 ret = pti->phy_prep(&p->phy, adapter, p->phy.mdio.prtad, NULL); in t3_replay_prep_adapter()