Lines Matching refs:adapter
35 adapter_t *adapter; member
51 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, in tricn_write() argument
61 adapter->regs + A_ESPI_CMD_ADDR); in tricn_write()
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
65 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; in tricn_write()
69 pr_err("%s: TRICN write timed out\n", adapter->name); in tricn_write()
74 static int tricn_init(adapter_t *adapter) in tricn_init() argument
78 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
79 pr_err("%s: ESPI clock not ready\n", adapter->name); in tricn_init()
83 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
86 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init()
87 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init()
88 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init()
91 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init()
93 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init()
95 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init()
96 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init()
97 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1); in tricn_init()
98 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1); in tricn_init()
99 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80); in tricn_init()
100 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1); in tricn_init()
103 adapter->regs + A_ESPI_RX_RESET); in tricn_init()
110 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
119 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; in t1_espi_intr_enable()
120 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
126 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
127 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
133 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
135 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
136 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
141 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
160 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
167 if (status && t1_is_T1B(espi->adapter)) in t1_espi_intr_handler()
169 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
178 static void espi_setup_for_pm3393(adapter_t *adapter) in espi_setup_for_pm3393() argument
180 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200; in espi_setup_for_pm3393()
182 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_pm3393()
183 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_pm3393()
184 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_pm3393()
185 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); in espi_setup_for_pm3393()
186 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_pm3393()
187 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_pm3393()
188 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_pm3393()
189 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_pm3393()
190 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); in espi_setup_for_pm3393()
193 static void espi_setup_for_vsc7321(adapter_t *adapter) in espi_setup_for_vsc7321() argument
195 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_vsc7321()
196 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_vsc7321()
197 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_vsc7321()
198 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_vsc7321()
199 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_vsc7321()
200 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_vsc7321()
201 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); in espi_setup_for_vsc7321()
203 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_vsc7321()
209 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports) in espi_setup_for_ixf1010() argument
211 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_ixf1010()
213 if (is_T2(adapter)) { in espi_setup_for_ixf1010()
214 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
215 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
217 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
218 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
221 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
222 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
224 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); in espi_setup_for_ixf1010()
231 adapter_t *adapter = espi->adapter; in t1_espi_init() local
234 writel(0, adapter->regs + A_ESPI_TRAIN); in t1_espi_init()
236 if (is_T2(adapter)) { in t1_espi_init()
239 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
241 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
243 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
246 espi_setup_for_pm3393(adapter); in t1_espi_init()
248 espi_setup_for_vsc7321(adapter); in t1_espi_init()
251 espi_setup_for_ixf1010(adapter, nports); in t1_espi_init()
256 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); in t1_espi_init()
258 if (is_T2(adapter)) { in t1_espi_init()
259 tricn_init(adapter); in t1_espi_init()
264 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
267 if (adapter->params.nports == 1) in t1_espi_init()
269 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
281 struct peespi *t1_espi_create(adapter_t *adapter) in t1_espi_create() argument
286 espi->adapter = adapter; in t1_espi_create()
291 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
293 struct peespi *espi = adapter->espi;
295 if (!is_T2(adapter))
300 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
305 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) in t1_espi_get_mon() argument
307 struct peespi *espi = adapter->espi; in t1_espi_get_mon()
310 if (!is_T2(adapter)) in t1_espi_get_mon()
322 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
323 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
324 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
326 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
336 int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait) in t1_espi_get_mon_t204() argument
338 struct peespi *espi = adapter->espi; in t1_espi_get_mon_t204()
339 u8 i, nport = (u8)adapter->params.nports; in t1_espi_get_mon_t204()
350 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
355 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
357 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon_t204()
360 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()