Lines Matching refs:mix_ctl
519 union cvmx_mixx_ctl mix_ctl; in octeon_mgmt_reset_hw() local
523 mix_ctl.u64 = 0; in octeon_mgmt_reset_hw()
524 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_reset_hw()
526 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); in octeon_mgmt_reset_hw()
527 } while (mix_ctl.s.busy); in octeon_mgmt_reset_hw()
528 mix_ctl.s.reset = 1; in octeon_mgmt_reset_hw()
529 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_reset_hw()
969 union cvmx_mixx_ctl mix_ctl; in octeon_mgmt_open() local
1008 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); in octeon_mgmt_open()
1011 if (mix_ctl.s.reset) { in octeon_mgmt_open()
1012 mix_ctl.s.reset = 0; in octeon_mgmt_open()
1013 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_open()
1015 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); in octeon_mgmt_open()
1016 } while (mix_ctl.s.reset); in octeon_mgmt_open()
1062 mix_ctl.u64 = 0; in octeon_mgmt_open()
1063 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */ in octeon_mgmt_open()
1064 mix_ctl.s.en = 1; /* Enable the port */ in octeon_mgmt_open()
1065 mix_ctl.s.nbtarb = 0; /* Arbitration mode */ in octeon_mgmt_open()
1067 mix_ctl.s.mrq_hwm = 1; in octeon_mgmt_open()
1069 mix_ctl.s.lendian = 1; in octeon_mgmt_open()
1071 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_open()